A 50 Gb/s Adaptive ADFE with SNR based power management for 2-PAM systems

Chee Kit Ng, Yu Chun Lin, Shyh Jye Jou

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

A 50Gb/s all-digital adaptive noise-suppression (NS) feed-forward equalizer (AFFE) and adaptive decision feedback equalizer (ADFE) for 2-level pulse amplitude modulation (2-PAM) serial link systems with SNR based power management scheme is presented. Based on a parallel extended incremental coefficientslookahead scheme (EICL), we propose a reconfigurable Dual Datapaths Self-Lookahead Filter (DD-SLF) for ADFE. SNR-power management skill is adopted to adaptively adjust the hardware configuration in different channel environment and SNR to achieve optimum energy efficiency. The whole equalizer which operates at 1 GHz system clock rate with 50 parallelisms is implemented in 40nm CMOS technology with a core area 0.38mm2. The equalizer with 50Gb/s throughput rate achieves 2.6pJ/bit energy efficiency under 0.81V supply measurement results.

Original languageEnglish
Title of host publication2019 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2019
PublisherInstitute of Electrical and Electronics Engineers Inc.
ISBN (Electronic)9781728106557
DOIs
StatePublished - Apr 2019
Event2019 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2019 - Hsinchu, Taiwan
Duration: 22 Apr 201925 Apr 2019

Publication series

Name2019 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2019

Conference

Conference2019 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2019
CountryTaiwan
CityHsinchu
Period22/04/1925/04/19

Keywords

  • 2-PAM digital adaptive decision feedback equalizer
  • Serial link
  • SNR power management

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    Ng, C. K., Lin, Y. C., & Jou, S. J. (2019). A 50 Gb/s Adaptive ADFE with SNR based power management for 2-PAM systems. In 2019 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2019 [8741878] (2019 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2019). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/VLSI-DAT.2019.8741878