A 5-GHz differential low-noise amplifier with high pin-to-pin ESD robustness in a 130-nm CMOS process

Yuan Wen Hsiao*, Ming-Dou Ker

*Corresponding author for this work

Research output: Contribution to journalArticlepeer-review

12 Scopus citations

Abstract

Two electrostatic discharge (ESD)-protected 5-GHz differential low-noise amplifiers (LNAs) are presented with consideration of pin-to-pin ESD protection. The pin-to-pin ESD issue for differential LNAs is addressed for the first time in the literature. Fabricated in a 130-nm CMOS process, both ESD-protected LNAs consume 10.3 mW under 1.2-V power supply. The first LNA with double-diode ESD protection scheme exhibits the power gain of 17.9 dB and noise figure of 2.43 dB at 5 GHz. Its human-body-model (HBM) and machine-model (MM) ESD levels are 2.5 kV and 200 V, respectively. With the same total parasitic capacitance from ESD protection devices, the second LNA with the proposed double silicon-controlled rectifier (SCR) ESD protection scheme has 6.5-kV HBM and 500-VMM ESD robustness, 17.9-dB power gain, and 2.54-dB noise figure at 5 GHz. The ESD test results have shown that the pin-to-pin ESD test is the most critical ESD-test pin combination for the conventional double-diode ESD protection scheme. With the proposed double-SCR ESD protection scheme, the pin-to-pin ESD robustness can be significantly improved without degrading RF performance. Experimental results have shown that the ESD protection circuit for LNA can be co-designed with the input matching network to simultaneously achieve excellent ESD robustness and RF performance.

Original languageEnglish
Article number4814540
Pages (from-to)1044-1053
Number of pages10
JournalIEEE Transactions on Microwave Theory and Techniques
Volume57
Issue number1
DOIs
StatePublished - 1 Jan 2009

Keywords

  • Electrostatic discharge (ESD)
  • Low-noise amplifier (LNA)
  • Power-rail ESD clamp circuit
  • RF integrated circuit (RF IC)
  • Silicon-controlled rectifier (SCR)
  • Substrate-triggered technique

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