A 5-GHz CMOS double-quadrature receiver front-end with single-stage quadrature generator

Chung-Yu Wu; Chung Yun Chou

doi:10.1109/JSSC.2003.822779

A 5-GHz CMOS double-quadrature receiver front-end with single-stage quadrature generator

Chung-Yu Wu^*, Chung Yun Chou

^*Corresponding author for this work

Department of Electronics Engineering

Research output: Contribution to journal › Article › peer-review

25 Scopus citations

Abstract

A 5-GHz CMOS double-quadrature front-end receiver for wireless LAN application is proposed. In the receiver, a one-stage RLC phase shifter is used to generate quadrature RF signals. Implemented in 0.18 μm CMOS technology, the receiver chip can achieve 50.6-dB image rejection with power dissipation of 22.4 mW at 1.8-V voltage supply.

Original language	English
Pages (from-to)	519-521
Number of pages	3
Journal	IEEE Journal of Solid-State Circuits
Volume	39
Issue number	3
DOIs	https://doi.org/10.1109/JSSC.2003.822779
State	Published - 1 Mar 2004

Keywords

CMOS technology
Double-quadrature architecture
IEEE 802.11a
Low-noise amplifier
Quadrature generator
Quadrature voltage-controlled oscillator
Radio frequency
Receiver

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abstract = "A 5-GHz CMOS double-quadrature front-end receiver for wireless LAN application is proposed. In the receiver, a one-stage RLC phase shifter is used to generate quadrature RF signals. Implemented in 0.18 μm CMOS technology, the receiver chip can achieve 50.6-dB image rejection with power dissipation of 22.4 mW at 1.8-V voltage supply.",

keywords = "CMOS technology, Double-quadrature architecture, IEEE 802.11a, Low-noise amplifier, Quadrature generator, Quadrature voltage-controlled oscillator, Radio frequency, Receiver",

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KW - CMOS technology

KW - Double-quadrature architecture

KW - IEEE 802.11a

KW - Low-noise amplifier

KW - Quadrature generator

KW - Quadrature voltage-controlled oscillator

KW - Radio frequency

KW - Receiver

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