A 5-GHz CMOS double-quadrature front-end receiver for wireless LAN application is proposed. In the receiver, a one-stage RLC phase shifter is used to generate quadrature RF signals. Implemented in 0.18 μm CMOS technology, the receiver chip can achieve 50.6-dB image rejection with power dissipation of 22.4 mW at 1.8-V voltage supply.
- CMOS technology
- Double-quadrature architecture
- IEEE 802.11a
- Low-noise amplifier
- Quadrature generator
- Quadrature voltage-controlled oscillator
- Radio frequency