@inproceedings{7147dcefd1214757bfc1e1c5285a3dc0,
title = "A 45nm dual-port SRAM with write and read capability enhancement at low voltage",
abstract = "This paper presents circuit techniques to improve write and read capability for dual-port SRAM design fabricated in a 45nm low-power process. The write capability is enhanced by negative write biasing without any reduction in the cell current for the other port. The result shows 12% better improvement with just 1.9% area overhead. This technique has been verified successfully on 65nm and 45nm SRAM chip and improved 120mV lower at 95% yield of minimum operation voltage than a conventional one. The read capability is enhanced by cell current boosting and word line voltage lowering schemes. The SNM is also enhanced significantly. The target is to work below 0.8V with the worst process corner variation.",
author = "Wang, {D. P.} and Liao, {H. J.} and H. Yamauchi and Chen, {Y. H.} and Lin, {Y. L.} and Lin, {S. H.} and Liu, {D. C.} and Chang, {H. C.} and Wei Hwang",
year = "2007",
month = dec,
day = "1",
doi = "10.1109/SOCC.2007.4545460",
language = "English",
isbn = "9781424415922",
series = "Proceedings - 20th Anniversary IEEE International SOC Conference",
pages = "211--214",
booktitle = "Proceedings - 20th Anniversary IEEE International SOC Conference",
note = "null ; Conference date: 26-09-2007 Through 29-09-2007",
}