A 45nm dual-port SRAM with write and read capability enhancement at low voltage

D. P. Wang; H. J. Liao; H. Yamauchi; Y. H. Chen; Y. L. Lin; S. H. Lin; D. C. Liu; H. C. Chang; Wei Hwang

doi:10.1109/SOCC.2007.4545460

A 45nm dual-port SRAM with write and read capability enhancement at low voltage

D. P. Wang, H. J. Liao, H. Yamauchi, Y. H. Chen, Y. L. Lin, S. H. Lin, D. C. Liu, H. C. Chang, Wei Hwang

Department of Electronics Engineering

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

45 Scopus citations

Abstract

This paper presents circuit techniques to improve write and read capability for dual-port SRAM design fabricated in a 45nm low-power process. The write capability is enhanced by negative write biasing without any reduction in the cell current for the other port. The result shows 12% better improvement with just 1.9% area overhead. This technique has been verified successfully on 65nm and 45nm SRAM chip and improved 120mV lower at 95% yield of minimum operation voltage than a conventional one. The read capability is enhanced by cell current boosting and word line voltage lowering schemes. The SNM is also enhanced significantly. The target is to work below 0.8V with the worst process corner variation.

Original language	English
Title of host publication	Proceedings - 20th Anniversary IEEE International SOC Conference
Pages	211-214
Number of pages	4
DOIs	https://doi.org/10.1109/SOCC.2007.4545460
State	Published - 1 Dec 2007
Event	20th Anniversary IEEE International SOC Conference - Hsinchu, Taiwan Duration: 26 Sep 2007 → 29 Sep 2007

Publication series

Name	Proceedings - 20th Anniversary IEEE International SOC Conference

Conference

Conference	20th Anniversary IEEE International SOC Conference
Country	Taiwan
City	Hsinchu
Period	26/09/07 → 29/09/07

Access to Document

10.1109/SOCC.2007.4545460

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Wang, D. P., Liao, H. J., Yamauchi, H., Chen, Y. H., Lin, Y. L., Lin, S. H., Liu, D. C., Chang, H. C., & Hwang, W. (2007). A 45nm dual-port SRAM with write and read capability enhancement at low voltage. In Proceedings - 20th Anniversary IEEE International SOC Conference (pp. 211-214). [4545460] (Proceedings - 20th Anniversary IEEE International SOC Conference). https://doi.org/10.1109/SOCC.2007.4545460

@inproceedings{7147dcefd1214757bfc1e1c5285a3dc0,

title = "A 45nm dual-port SRAM with write and read capability enhancement at low voltage",

abstract = "This paper presents circuit techniques to improve write and read capability for dual-port SRAM design fabricated in a 45nm low-power process. The write capability is enhanced by negative write biasing without any reduction in the cell current for the other port. The result shows 12% better improvement with just 1.9% area overhead. This technique has been verified successfully on 65nm and 45nm SRAM chip and improved 120mV lower at 95% yield of minimum operation voltage than a conventional one. The read capability is enhanced by cell current boosting and word line voltage lowering schemes. The SNM is also enhanced significantly. The target is to work below 0.8V with the worst process corner variation.",

author = "Wang, {D. P.} and Liao, {H. J.} and H. Yamauchi and Chen, {Y. H.} and Lin, {Y. L.} and Lin, {S. H.} and Liu, {D. C.} and Chang, {H. C.} and Wei Hwang",

year = "2007",

month = dec,

day = "1",

doi = "10.1109/SOCC.2007.4545460",

language = "English",

isbn = "9781424415922",

series = "Proceedings - 20th Anniversary IEEE International SOC Conference",

pages = "211--214",

booktitle = "Proceedings - 20th Anniversary IEEE International SOC Conference",

note = "null ; Conference date: 26-09-2007 Through 29-09-2007",

}

Wang, DP, Liao, HJ, Yamauchi, H, Chen, YH, Lin, YL, Lin, SH, Liu, DC, Chang, HC & Hwang, W 2007, A 45nm dual-port SRAM with write and read capability enhancement at low voltage. in Proceedings - 20th Anniversary IEEE International SOC Conference., 4545460, Proceedings - 20th Anniversary IEEE International SOC Conference, pp. 211-214, 20th Anniversary IEEE International SOC Conference, Hsinchu, Taiwan, 26/09/07. https://doi.org/10.1109/SOCC.2007.4545460

A 45nm dual-port SRAM with write and read capability enhancement at low voltage. / Wang, D. P.; Liao, H. J.; Yamauchi, H.; Chen, Y. H.; Lin, Y. L.; Lin, S. H.; Liu, D. C.; Chang, H. C.; Hwang, Wei.

Proceedings - 20th Anniversary IEEE International SOC Conference. 2007. p. 211-214 4545460 (Proceedings - 20th Anniversary IEEE International SOC Conference).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

TY - GEN

T1 - A 45nm dual-port SRAM with write and read capability enhancement at low voltage

AU - Wang, D. P.

AU - Liao, H. J.

AU - Yamauchi, H.

AU - Chen, Y. H.

AU - Lin, Y. L.

AU - Lin, S. H.

AU - Liu, D. C.

AU - Chang, H. C.

AU - Hwang, Wei

PY - 2007/12/1

Y1 - 2007/12/1

N2 - This paper presents circuit techniques to improve write and read capability for dual-port SRAM design fabricated in a 45nm low-power process. The write capability is enhanced by negative write biasing without any reduction in the cell current for the other port. The result shows 12% better improvement with just 1.9% area overhead. This technique has been verified successfully on 65nm and 45nm SRAM chip and improved 120mV lower at 95% yield of minimum operation voltage than a conventional one. The read capability is enhanced by cell current boosting and word line voltage lowering schemes. The SNM is also enhanced significantly. The target is to work below 0.8V with the worst process corner variation.

AB - This paper presents circuit techniques to improve write and read capability for dual-port SRAM design fabricated in a 45nm low-power process. The write capability is enhanced by negative write biasing without any reduction in the cell current for the other port. The result shows 12% better improvement with just 1.9% area overhead. This technique has been verified successfully on 65nm and 45nm SRAM chip and improved 120mV lower at 95% yield of minimum operation voltage than a conventional one. The read capability is enhanced by cell current boosting and word line voltage lowering schemes. The SNM is also enhanced significantly. The target is to work below 0.8V with the worst process corner variation.

UR - http://www.scopus.com/inward/record.url?scp=51049094640&partnerID=8YFLogxK

U2 - 10.1109/SOCC.2007.4545460

DO - 10.1109/SOCC.2007.4545460

M3 - Conference contribution

AN - SCOPUS:51049094640

SN - 9781424415922

T3 - Proceedings - 20th Anniversary IEEE International SOC Conference

SP - 211

EP - 214

BT - Proceedings - 20th Anniversary IEEE International SOC Conference

Y2 - 26 September 2007 through 29 September 2007

ER -