A 45nm dual-port SRAM with write and read capability enhancement at low voltage

D. P. Wang, H. J. Liao, H. Yamauchi, Y. H. Chen, Y. L. Lin, S. H. Lin, D. C. Liu, H. C. Chang, Wei Hwang

Research output: Chapter in Book/Report/Conference proceedingConference contribution

45 Scopus citations

Abstract

This paper presents circuit techniques to improve write and read capability for dual-port SRAM design fabricated in a 45nm low-power process. The write capability is enhanced by negative write biasing without any reduction in the cell current for the other port. The result shows 12% better improvement with just 1.9% area overhead. This technique has been verified successfully on 65nm and 45nm SRAM chip and improved 120mV lower at 95% yield of minimum operation voltage than a conventional one. The read capability is enhanced by cell current boosting and word line voltage lowering schemes. The SNM is also enhanced significantly. The target is to work below 0.8V with the worst process corner variation.

Original languageEnglish
Title of host publicationProceedings - 20th Anniversary IEEE International SOC Conference
Pages211-214
Number of pages4
DOIs
StatePublished - 1 Dec 2007
Event20th Anniversary IEEE International SOC Conference - Hsinchu, Taiwan
Duration: 26 Sep 200729 Sep 2007

Publication series

NameProceedings - 20th Anniversary IEEE International SOC Conference

Conference

Conference20th Anniversary IEEE International SOC Conference
CountryTaiwan
CityHsinchu
Period26/09/0729/09/07

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    Wang, D. P., Liao, H. J., Yamauchi, H., Chen, Y. H., Lin, Y. L., Lin, S. H., Liu, D. C., Chang, H. C., & Hwang, W. (2007). A 45nm dual-port SRAM with write and read capability enhancement at low voltage. In Proceedings - 20th Anniversary IEEE International SOC Conference (pp. 211-214). [4545460] (Proceedings - 20th Anniversary IEEE International SOC Conference). https://doi.org/10.1109/SOCC.2007.4545460