A 45 nm 10T dual-port SRAM with shared bit-line scheme for low power operation

Dao Ping Wang, Wei Hwang*

*Corresponding author for this work

Research output: Contribution to journalArticlepeer-review


This paper proposes a 10T bit-cell of dual-port (DP) SRAM design to improve Static Noise Margin (SNM) and solve write/read disturb issues in nano-scale CMOS technologies. In additional used the row access transistor in the bit-cell, adding Y-access MOS (column-direction access transistor) can improve dummy-read cells' noise margin and isolate the pre-charge noise from bit-lines in synchronous or asynchronous clock operation. The paper a also proposes a scheme of combining the row access transistor and sharing bit-line with an adjacent bit-cell. This scheme can reduce the bit-line number to half and mitigate the current consumption of the write/read buffer caused by pre-charging the bit-line to VDD. Furthermore, 2 -passgate (column direction access transistor) numbers can also be reduced to half with the proposed DP 10T SRAM architecture. The result shows that write/read buffer current consumption was reduced by over 30%, compared to the conventional DP 8T structure from 1.4 V to 0.6 V VDD.

Original languageEnglish
Pages (from-to)472-484
Number of pages13
JournalJournal of Low Power Electronics
Issue number4
StatePublished - 1 Aug 2012


  • 10T
  • Dual-Port
  • SRAM
  • Write/Read Disturb

Fingerprint Dive into the research topics of 'A 45 nm 10T dual-port SRAM with shared bit-line scheme for low power operation'. Together they form a unique fingerprint.

Cite this