A 4.2 nW and 18 ppm/°C temperature coefficient leakage-based square root compensation (LSRC) CMOS voltage reference

Chao Jen Huang, Yan Jiun Lai, Yu Jheng Ou Yang, Hung Wei Chen, Chun Chieh Kuo, Ke-Horng Chen*, Ying Hsi Lin, Shian Ru Lin, Tsung Yen Tsai

*Corresponding author for this work

Research output: Contribution to journalArticle

2 Scopus citations

Abstract

State-of-the-art CMOS-based voltage reference suffer from a trade-off between power dissipation and temperature coefficient (TC) due to the limited order of compensation in an advanced process which features a low supplied voltage (11.2 V). The proposed voltage reference with leakage-based square root compensation (LSRC) technique bias the substrate to offset TC with ultra-low leakage current (100300 pA). On the other hand, the architecture provides an extensible order of compensation which is independent of voltage headroom. The two LSRC branches voltage reference implemented in 40 nm CMOS process achieves a within-wafer σ/μ of 0.204 and a TC of 18 ppm/°C with a power consumption of 4.2 nW.

Original languageEnglish
Article number8676347
Pages (from-to)728-732
Number of pages5
JournalIEEE Transactions on Circuits and Systems II: Express Briefs
Volume66
Issue number5
DOIs
StatePublished - 1 May 2019

Keywords

  • Temperature coefficient (TC) compensation
  • leakage-based square root compensation (LSRC) technique
  • low power consumption

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