A 40nm 256kb 6T SRAM with threshold power-gating, low-swing global read bit-line, and charge-sharing write with Vtrip-tracking and negative source-line write-assists

Chao Kuei Chung, Chien Yu Lu, Zhi Hao Chang, Shyh-Jye Jou, Ching Te Chuang, Ming Hsien Tu, Yu Hsuan Chen, Yong Jyun Hu, Paul Sen Kan, Huan Shun Huang, Kuen Di Lee, Yung Shin Kao

Research output: Chapter in Book/Report/Conference proceedingConference contribution

1 Scopus citations

Abstract

This paper presents a 256kb 6T static random access memory (SRAM) with threshold power-gating (TPG), low-swing global read bit-line (GRBL), and charge-sharing write with Vtrip (VTP) tracking and negative source-line (NVSL) write-assists (WA). The TPG facilitates lower NAP mode voltage/power and faster wake-up for the cell array, while low-swing GRBL reduces the dynamic read power. A variation-tolerant charge-sharing write scheme, where the floating 'Low' global write bit-line (GWBL) is used to capacitively couple down the local bit-line (LBL), is combined with a cell Vtrip-tracking and NVSL write-assists to improve the write-ability. The 256kb test chip is implemented in UMC 40nm low-power (LP) CMOS technology. Error-free full-functionality is achieved from 1.18GHz at 1.5V to 100MHz at 0.65V without redundancy. The TPG scheme reduces the power by 70% (55%) at 1.5V (0.5V) in NAP mode. The low-swing GRBL reduces dynamic read power by 3.5% (8%) at 1.1V (0.65V). The VTP-WA and NVSL-WA improve the write VMIN by 50mV (from 0.7V to 0.65V) and reduce write bit failure rate by 2.75× at 0.65V.

Original languageEnglish
Title of host publicationInternational System on Chip Conference
EditorsRamalingam Sridhar, Danella Zhao, Kaijian Shi, Thomas Buchner
PublisherIEEE Computer Society
Pages455-460
Number of pages6
ISBN (Electronic)9781479933785
DOIs
StatePublished - 5 Nov 2014
Event27th IEEE International System on Chip Conference, SOCC 2014 - Las Vegas, United States
Duration: 2 Sep 20145 Sep 2014

Publication series

NameInternational System on Chip Conference
ISSN (Print)2164-1676
ISSN (Electronic)2164-1706

Conference

Conference27th IEEE International System on Chip Conference, SOCC 2014
CountryUnited States
CityLas Vegas
Period2/09/145/09/14

Keywords

  • 6T SRAM
  • low power
  • power-gating
  • write-assist

Fingerprint Dive into the research topics of 'A 40nm 256kb 6T SRAM with threshold power-gating, low-swing global read bit-line, and charge-sharing write with Vtrip-tracking and negative source-line write-assists'. Together they form a unique fingerprint.

Cite this