A 40mW 3.5kΩ 3Gb/s CMOS differential transimpedance amplifier using negative-impedance compensation

Chia-Ming Tsai*, Wen Tsao Chen

*Corresponding author for this work

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

8 Scopus citations

Abstract

Combining the self-compensated topology with the negative-impedance- compensation technique, a differential TIA with enlarged input-capacitance tolerances is designed in a 0.18μm CMOS technology. The DR is measured to be >20dB without using any gain control. The complete TIA IC consumes 40mW from a 1.8V supply.

Original languageEnglish
Title of host publication2007 IEEE International Solid-State Circuits Conference, ISSCC - Digest of Technical Papers
DOIs
StatePublished - 27 Sep 2007
Event54th IEEE International Solid-State Circuits Conference, ISSCC 2007 - San Francisco, CA, United States
Duration: 11 Feb 200715 Feb 2007

Publication series

NameDigest of Technical Papers - IEEE International Solid-State Circuits Conference
ISSN (Print)0193-6530

Conference

Conference54th IEEE International Solid-State Circuits Conference, ISSCC 2007
CountryUnited States
CitySan Francisco, CA
Period11/02/0715/02/07

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