A 40 Gb/s PAM-4 Receiver with 2-Tap DFE Based on Automatically Non-Even Level Tracking

Chia Tse Hung, Yu Ping Huang, Wei-Zen Chen

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

Abstract

A 40 Gb/s PAM-4 receiver comprised of a continuous-time linear equalizer (CTLE) and 2-tap decision-feedback equalizers (DFE) based on a novel level tracking circuit (ANLT) is proposed. A sign-sign LMS engine is embedded for the DFE and ANLT coefficients adaptation to accommodate different channel loss. The ANLT is capable of automatically tracking a non-evenly spaced PAM-4 signal, allowing the receiver to demodulate a distorted input with 2-bit flash ADCs. Fabricated in a TSMC 40nm CMOS technology, the whole receiver consumes 241.8 mW at 40 Gb/s operation. Core area is 0.274mm 2 .

Original languageEnglish
Title of host publication2018 IEEE Asian Solid-State Circuits Conference, A-SSCC 2018 - Proceedings
PublisherInstitute of Electrical and Electronics Engineers Inc.
Pages213-214
Number of pages2
ISBN (Electronic)9781538664124
DOIs
StatePublished - 14 Dec 2018
Event2018 IEEE Asian Solid-State Circuits Conference, A-SSCC 2018 - Tainan, Taiwan
Duration: 5 Nov 20187 Nov 2018

Publication series

Name2018 IEEE Asian Solid-State Circuits Conference, A-SSCC 2018 - Proceedings

Conference

Conference2018 IEEE Asian Solid-State Circuits Conference, A-SSCC 2018
CountryTaiwan
CityTainan
Period5/11/187/11/18

Keywords

  • automatically non-even level tracking (ANLT)
  • continuous-time linear equalizer (CTLE)
  • decision-feedback equalizer (DFE)
  • Pulse-amplitude modulation (PAM)
  • sign-sign least mean square (SS-LMS)

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