A 40 Gbps optical receiver analog front-end in 65 nm CMOS

Shun Tien Chou*, Shih Hao Huang, Zheng Hao Hong, Wei-Zen Chen

*Corresponding author for this work

Research output: Contribution to conferencePaperpeer-review

12 Scopus citations

Abstract

A 40 Gbps optical receiver analog front end integrating a trans-impedance amplifier (TIA) and a limiting amplifier is presented. To achieve wide band operation, nested feedback TIA and interleaving post amplifier with split series-peaking are proposed in this design. This receiver provides the transimpedance of 92 dBOhm, input-referred noise of 14 pA/Hz, 3dB bandwidth of 35 GHz, and 800mV pp differential output voltage swing. The total power dissipation is 168 mW from 1.2-V supply. Fabricated in a 65 nm CMOS technology, the chip size is 0.825mm 2.

Original languageEnglish
Pages1736-1739
Number of pages4
DOIs
StatePublished - 28 Sep 2012
Event2012 IEEE International Symposium on Circuits and Systems, ISCAS 2012 - Seoul, Korea, Republic of
Duration: 20 May 201223 May 2012

Conference

Conference2012 IEEE International Symposium on Circuits and Systems, ISCAS 2012
CountryKorea, Republic of
CitySeoul
Period20/05/1223/05/12

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