A 38mW 40Gb/s 4-lane tri-band PAM-4 / 16-QAM transceiver in 28nm CMOS for high-speed Memory interface

Wei Han Cho, Yilei Li, Yuan Du, Chien Heng Wong, Jieqiong Du, Po-Tsang Huang, Sheau Jiung Lee, Huan Neng Chen, Chewn Pu Jou, Fu Lung Hsueh, Mau-Chung Chang

Research output: Chapter in Book/Report/Conference proceedingConference contribution

10 Scopus citations

Abstract

The continuous scaling of CMOS technology increases processor performance and memory capacity, requiring the CPU/Memory interface to have ever-higher bandwidth and energy efficiency over the past few years. Among those cutting-edge interface technologies, multi-band (multi-tone) signaling has shown great potential because of its high data-rate capability along with its low energy consumption [3]-[5]. With spectrally divided signaling, the multi-band transceiver can be designed to avoid spectral notches with extended communication bandwidth of multi-drop buses [4]. Also, its unique self-equalized double-sideband signaling renders the multi-band transceiver immune to inter-symbol interference caused by channel attenuation without additional equalization circuitry [5]. To further improve the capability and validate the scalability of multi-band signaling, we have realized a tri-band transceiver with four parallel lanes and achieved a total data rate of 40Gb/s, with total power consumption of 38mW in 28nm CMOS technology.

Original languageEnglish
Title of host publication2016 IEEE International Solid-State Circuits Conference, ISSCC 2016
PublisherInstitute of Electrical and Electronics Engineers Inc.
Pages184-185
Number of pages2
ISBN (Electronic)9781467394666
DOIs
StatePublished - 23 Feb 2016
Event63rd IEEE International Solid-State Circuits Conference, ISSCC 2016 - San Francisco, United States
Duration: 31 Jan 20164 Feb 2016

Publication series

NameDigest of Technical Papers - IEEE International Solid-State Circuits Conference
Volume59
ISSN (Print)0193-6530

Conference

Conference63rd IEEE International Solid-State Circuits Conference, ISSCC 2016
CountryUnited States
CitySan Francisco
Period31/01/164/02/16

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    Cho, W. H., Li, Y., Du, Y., Wong, C. H., Du, J., Huang, P-T., Lee, S. J., Chen, H. N., Jou, C. P., Hsueh, F. L., & Chang, M-C. (2016). A 38mW 40Gb/s 4-lane tri-band PAM-4 / 16-QAM transceiver in 28nm CMOS for high-speed Memory interface. In 2016 IEEE International Solid-State Circuits Conference, ISSCC 2016 (pp. 184-185). [7417968] (Digest of Technical Papers - IEEE International Solid-State Circuits Conference; Vol. 59). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/ISSCC.2016.7417968