A 3.84 Gbits/s AES crypto coprocessor with modes of operation in a 0.18-μm CMOS technology

Alireza Hodjat*, David D. Hwang, Bo-Cheng Lai, Kris Tiri, Ingrid Verbauwhede

*Corresponding author for this work

Research output: Contribution to conferencePaperpeer-review

50 Scopus citations

Abstract

In this paper an AES crypto coprocessor that is fabricated using a 0.18-μm CMOS technology is presented. This crypto coprocessor performs the AES-128 encryption in both feedback and non-feedback modes of operation. A maximum throughput of 3.84 Gbits/s is achieved at a 330 MHz clock frequency for ECB, OFB, and CBC modes of operation. This crypto coprocessor can be programmed using the memory-mapped interface of an embedded CPU core and is tested using a LEON 32-bit (SPARC V8) processor in the ThumbPod secure system-on-chip.

Original languageEnglish
Pages60-63
Number of pages4
DOIs
StatePublished - 29 Dec 2005
Event2005 ACM Great Lakessymposium on VLSI, GLSVLSI'05 - Chicago, IL, United States
Duration: 17 Apr 200519 Apr 2005

Conference

Conference2005 ACM Great Lakessymposium on VLSI, GLSVLSI'05
CountryUnited States
CityChicago, IL
Period17/04/0519/04/05

Keywords

  • ASIC
  • Advanced Encryption Standard (AES)
  • Crypto-processor
  • Cryptography
  • FPGA
  • Hardware architectures
  • Security
  • VLSI

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