A 36-mW continuous-time sigma-delta modulator with 74db dynamic range and 10-MHz bandwidth

Kuo Che Hong*, Her-Ming Chiueh

*Corresponding author for this work

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

Abstract

A wide-bandwidth low-power CT ΣΔ modulator with 10MHz signal bandwidth is implemented in TSMC 0.18 μm CMOS process in this paper. To realize such application scenario, the proposed modulator comprises a third-order active-RC loop filter and a 4-bit internal quantizer operating at 320 MHz clock frequency. To reduced clock jitter sensitivity, non-return-to-zero (NRZ) DAC pulse shaping is used. The excess loop delay is set to half the sampling period of the quantizer and the excess loop delay compensation is achieved by the discrete-time deviator structure. The simulation result achieves above 74-dB SNDR (12 ENOB) over a 10-MHz signal band. The power dissipation is 36mW from a 1.8-V supply and the energy per conversion is 235fJ from post-layout simulation. The proposed circuitry can be utilized in low-power medical imaging and modern wireless communications.

Original languageEnglish
Title of host publicationProceedings of the 2010 18th IEEE/IFIP International Conference on VLSI and System-on-Chip, VLSI-SoC 2010
Pages392-395
Number of pages4
DOIs
StatePublished - 1 Dec 2010
Event2010 18th IEEE/IFIP International Conference on VLSI and System-on-Chip, VLSI-SoC 2010 - Madrid, Spain
Duration: 27 Sep 201029 Sep 2010

Publication series

NameProceedings of the 2010 18th IEEE/IFIP International Conference on VLSI and System-on-Chip, VLSI-SoC 2010

Conference

Conference2010 18th IEEE/IFIP International Conference on VLSI and System-on-Chip, VLSI-SoC 2010
CountrySpain
CityMadrid
Period27/09/1029/09/10

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