A 3.52 Gb/s mmWave baseband with delayed decision feedback sequence estimation in 40 nm

Nicholas Preyss, Christian Senning, Andreas Burg, Wei Chang Liu, Chun Yi Liu, Shyh-Jye Jou

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

We present a digital baseband ASIC for 60 GHz single-carrier (SC) transmission that is optimized for communication scenarios in which most of the energy is concentrated in the first few channel taps. Such scenarios occur for example in office environments with strong reflections. Our circuit targets close-to-optimum maximum-likelihood performance under such conditions. To this end, we show for the first time how a reduced-state-sequence-estimation algorithm can be realized for the 1760 MHz bandwidth of the IEEE 802.11ad standard. The equalizer is complemented in the frontend by a synchronization unit for frequency offset compensation as well as a Golay-sequence based channel estimator and in the backend by an low density parity check (LDPC) decoder. In 40nm CMOS we achieve a measured data rate of up to 3.52 Gb/s using QPSK modulation.

Original languageEnglish
Title of host publication2015 IEEE Asian Solid-State Circuits Conference, A-SSCC 2015 - Proceedings
PublisherInstitute of Electrical and Electronics Engineers Inc.
ISBN (Electronic)9781467371919
DOIs
StatePublished - 19 Jan 2016
Event11th IEEE Asian Solid-State Circuits Conference, A-SSCC 2015 - Xiamen, Fujian, China
Duration: 9 Nov 201511 Nov 2015

Publication series

Name2015 IEEE Asian Solid-State Circuits Conference, A-SSCC 2015 - Proceedings

Conference

Conference11th IEEE Asian Solid-State Circuits Conference, A-SSCC 2015
CountryChina
CityXiamen, Fujian
Period9/11/1511/11/15

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