A BiCMOS gate array with the gate delay of 350 ps has been realized by 0.8 μm BiCMOS technology. Minimum gate delay and minimum cell area have been achieved with a shared bipolar cell structure. The gate delay is almost equivalent to that of a 0.5 μm pure CMOS gate array. Cell area increase is minimized to only 25 % compared with a 0.8 μm pure CMOS cell. I/O cells can interface with CMOS, TIL and ECL chips at the same time with a single supply voltage of 5 V.
|Journal||Proceedings of the Custom Integrated Circuits Conference|
|State||Published - 1989|
|Event||11th IEEE 1989 Custom Integrated Circuits Conference, CICC'89 - San Diego, CA, United States|
Duration: 15 May 1989 → 18 May 1989