A 3.5-ns/77 K and 6.2-ns/300 K 64K CMOS RAM with ECL Interfaces

Terry I. Chappell, Stanley E. Schuster, Barbara A. Chappell, James W. Allan, Jack Y.C. Sun, Stephen P. Klepner, Robert L. Franch, Paul F. Greier, Phillip J. Restle

Research output: Contribution to journalArticle

7 Scopus citations

Abstract

This paper describes a 64K CMOS RAM with ECL interfaces having access times of 6.2 ns at room temperature and, with a CMOS process specifically optimized for low-temperature operation, 3.5 ns at liquid nitrogen (LN) temperature. The CMOS processes feature a 0.5-μm Lett, self-aligned TiSi2, double-level metal, and an average minimum feature size of 1.35 μm. Circuits key to high-speed operation are described with emphasis on low power and safe operation. Unique aspects of LN-temperature operation are discussed including circuit/device interactions, the impact of velocity saturation effects on channel length, temperature and power supply sensitivities, and the characteristics of the ECL-to-CMOS receiver circuits.

Original languageEnglish
Pages (from-to)859-868
Number of pages10
JournalIEEE Journal of Solid-State Circuits
Volume24
Issue number4
DOIs
StatePublished - Aug 1989

Fingerprint Dive into the research topics of 'A 3.5-ns/77 K and 6.2-ns/300 K 64K CMOS RAM with ECL Interfaces'. Together they form a unique fingerprint.

  • Cite this

    Chappell, T. I., Schuster, S. E., Chappell, B. A., Allan, J. W., Sun, J. Y. C., Klepner, S. P., Franch, R. L., Greier, P. F., & Restle, P. J. (1989). A 3.5-ns/77 K and 6.2-ns/300 K 64K CMOS RAM with ECL Interfaces. IEEE Journal of Solid-State Circuits, 24(4), 859-868. https://doi.org/10.1109/4.34062