A 3.5-Gb/s CMOS burst-mode laser driver with automatic power control using single power supply

Day Uei Li; Li Ren Huang; Chia-Ming Tsai

doi:10.1109/ISCAS.2005.1465882

A 3.5-Gb/s CMOS burst-mode laser driver with automatic power control using single power supply

Day Uei Li, Li Ren Huang, Chia-Ming Tsai

Department of Electronics Engineering

Research output: Contribution to journal › Conference article › peer-review

8 Scopus citations

Abstract

A 3.5-Gb/s burst-mode laser driver with automatic power control (APC) fabricated in 0.25um 1P5M CMOS process is presented. With the proposed waveform shaping circuit, the driver could operate under a single 3.3 V power supply without sacrificing the output headroom, and it could output 6mA to 60mA modulation current with negligible overshooting. Measurements on mounted chips show clear electrical eye diagrams operating over 3.5-Gb/s data rate with typical rise/fall times (20% to 80%) of 84/97ps. Moreover, optical eye diagram is also demonstrated by connecting the driver with a 1.25-Gb/s 1310nm laser diode. The laser turn on/off time is about 30/20ns, much less than the criteria (512ns) that IEEE 802.3ah standard has proposed.

Original language	English
Article number	1465882
Pages (from-to)	5501-5504
Number of pages	4
Journal	Proceedings - IEEE International Symposium on Circuits and Systems
DOIs	https://doi.org/10.1109/ISCAS.2005.1465882
State	Published - 1 Dec 2005
Event	IEEE International Symposium on Circuits and Systems 2005, ISCAS 2005 - Kobe, Japan Duration: 23 May 2005 → 26 May 2005

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10.1109/ISCAS.2005.1465882

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title = "A 3.5-Gb/s CMOS burst-mode laser driver with automatic power control using single power supply",

abstract = "A 3.5-Gb/s burst-mode laser driver with automatic power control (APC) fabricated in 0.25um 1P5M CMOS process is presented. With the proposed waveform shaping circuit, the driver could operate under a single 3.3 V power supply without sacrificing the output headroom, and it could output 6mA to 60mA modulation current with negligible overshooting. Measurements on mounted chips show clear electrical eye diagrams operating over 3.5-Gb/s data rate with typical rise/fall times (20% to 80%) of 84/97ps. Moreover, optical eye diagram is also demonstrated by connecting the driver with a 1.25-Gb/s 1310nm laser diode. The laser turn on/off time is about 30/20ns, much less than the criteria (512ns) that IEEE 802.3ah standard has proposed.",

author = "Li, {Day Uei} and Huang, {Li Ren} and Chia-Ming Tsai",

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AU - Tsai, Chia-Ming

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N2 - A 3.5-Gb/s burst-mode laser driver with automatic power control (APC) fabricated in 0.25um 1P5M CMOS process is presented. With the proposed waveform shaping circuit, the driver could operate under a single 3.3 V power supply without sacrificing the output headroom, and it could output 6mA to 60mA modulation current with negligible overshooting. Measurements on mounted chips show clear electrical eye diagrams operating over 3.5-Gb/s data rate with typical rise/fall times (20% to 80%) of 84/97ps. Moreover, optical eye diagram is also demonstrated by connecting the driver with a 1.25-Gb/s 1310nm laser diode. The laser turn on/off time is about 30/20ns, much less than the criteria (512ns) that IEEE 802.3ah standard has proposed.

AB - A 3.5-Gb/s burst-mode laser driver with automatic power control (APC) fabricated in 0.25um 1P5M CMOS process is presented. With the proposed waveform shaping circuit, the driver could operate under a single 3.3 V power supply without sacrificing the output headroom, and it could output 6mA to 60mA modulation current with negligible overshooting. Measurements on mounted chips show clear electrical eye diagrams operating over 3.5-Gb/s data rate with typical rise/fall times (20% to 80%) of 84/97ps. Moreover, optical eye diagram is also demonstrated by connecting the driver with a 1.25-Gb/s 1310nm laser diode. The laser turn on/off time is about 30/20ns, much less than the criteria (512ns) that IEEE 802.3ah standard has proposed.

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