A 3.46 Gb/s (9141,8224) LDPC-based ECC scheme and on-line channel estimation for solid-state drive applications

Kin Chu Ho, Chih Lung Chen, Yen Chin Liao, Hsie-Chia Chang, Chen-Yi Lee

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

7 Scopus citations

Abstract

As the reliability of NAND Flash memory keeps degrading, Low-Density Parity-Check (LDPC) codes are widely proposed to extend the endurance of Solid State Drive (SSD). However, implementing powerful decoding algorithm such as soft min-sum algorithm with high decoding speed comes along with higher hardware cost. To achieve efficient hardware cost, we propose a multi-strategy ECC scheme which consists of modified gradient descent bit-flipping (MGDBF), hard min-sum, and soft min-sum decoders. The MGDBF decoder aims to correct most of the erroneous codewords with advantages of high decoding throughput and low hardware cost, while the soft min-sum decoder is targeted to correct codewords with large number of errors under moderate decoding throughput and reasonable hardware cost. In addition, we propose a bi-sectional channel estimation technique which enables on-line estimation of distribution to generate accurate soft information for LDPC decoding with low complexity. The ECC codec and the complete Toggle DDR 1.0 NAND interface control circuits are integrated and fabricated in 90nm CMOS process. The throughput of proposed MGDBF decoder achieves 3.46 Gb/s which satisfies the throughput requirement of both toggle DDR 1.0 and 2.0 NAND interfaces.

Original languageEnglish
Title of host publication2015 IEEE International Symposium on Circuits and Systems, ISCAS 2015
PublisherInstitute of Electrical and Electronics Engineers Inc.
Pages1450-1453
Number of pages4
ISBN (Electronic)9781479983919
DOIs
StatePublished - 27 Jul 2015
EventIEEE International Symposium on Circuits and Systems, ISCAS 2015 - Lisbon, Portugal
Duration: 24 May 201527 May 2015

Publication series

NameProceedings - IEEE International Symposium on Circuits and Systems
Volume2015-July
ISSN (Print)0271-4310

Conference

ConferenceIEEE International Symposium on Circuits and Systems, ISCAS 2015
CountryPortugal
CityLisbon
Period24/05/1527/05/15

Keywords

  • LDPC codes
  • NAND Flash memory
  • Solid State Drive

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