This manuscript describes a 34-42GHz single-sideband 90nm-CMOS transmitter where PLL has been integrated into the LO chain and, with I/Q input and two-stage up-conversion, a 30dB image-rejection ratio is achieved within the intended bandwidth. This transmitter's wideband tuning range is made possible by the use of additional capacitor on the VCO, and the phase noise of the resulting RF output is in the range of-70 to-90dBc/Hz at 1MHz, and all below-100dBc/Hz at 10MHz. The circuit's IF-to-RF conversion gain is 30dB, with saturated output power around 5dBm, and the total power consumption is 260mW. Through the control of the power amplifier's drain bias, a 50dB power level difference can be obtained, thus allows signal modulation and further combination with the receiver. This 1100×650um
transmitter can be used as a prototypical circuit to explore next-generation mobile communication and civilian radar array systems.