A 3.33Gb/s (1200,720) low-density parity check code decoder

Chien Ching Lin*, Kai Li Lin, Hsie-Chia Chang, Chen-Yi Lee

*Corresponding author for this work

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

34 Scopus citations


In this paper, a (1200,720) LDPC decoder based on an irregular parity check matrix is presented. For achieving higher chip density and less critical path delay, the proposed architecture features a new data reordering such that only one specific data bus exists between message memories and computational units. Moreover, the LDPC decoder can also process two different codewords concurrently to increase throughput and datapath efficiency. After chip implementation, a 3.33Gb/s data rate is achieved with 8 decoding iterations in the 21.23mm2 0.18μm silicon area. The other 0.13μm chip with the 10.24mm2 core can further reach a 5.92Gb/s data rate under 1.02V supply.

Original languageEnglish
Title of host publicationProceedings of ESSCIRC 2005
Subtitle of host publication31st European Solid-State Circuits Conference
Number of pages4
StatePublished - 1 Dec 2005
EventESSCIRC 2005: 31st European Solid-State Circuits Conference - Grenoble, France
Duration: 12 Sep 200516 Sep 2005

Publication series

NameProceedings of ESSCIRC 2005: 31st European Solid-State Circuits Conference


ConferenceESSCIRC 2005: 31st European Solid-State Circuits Conference

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