A 33 mW 12-bit 100 MHz sample-and-hold amplifier

Cheng Chung Hsu, Jieh-Tsorng Wu

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

5 Scopus citations

Abstract

A high-speed high-resolution sample-and-hold amplifier (SHA) is designed for time-interleaved analog-to-digital converter applications. Using the techniques of precharging and output capacitor coupling can mitigate the requirements for the opamp, resulting in low power dissipation. Implemented in a standard 0.25 μm CMOS technology, the SHA achieves 73 dB SFDR for 2 Vpp input at 100 MHz sampling rate. The performance is not degraded for input frequency up to the Nyquist frequency. Power consumption is 33 mW from a single 2.5 V supply.

Original languageEnglish
Title of host publication2002 IEEE Asia-Pacific Conference on ASIC, AP-ASIC 2002 - Proceedings
PublisherInstitute of Electrical and Electronics Engineers Inc.
Pages169-172
Number of pages4
ISBN (Electronic)0780373634, 9780780373631
DOIs
StatePublished - 1 Jan 2002
Event3rd IEEE Asia-Pacific Conference on ASIC, AP-ASIC 2002 - Taipei, Taiwan
Duration: 6 Aug 20028 Aug 2002

Publication series

Name2002 IEEE Asia-Pacific Conference on ASIC, AP-ASIC 2002 - Proceedings

Conference

Conference3rd IEEE Asia-Pacific Conference on ASIC, AP-ASIC 2002
CountryTaiwan
CityTaipei
Period6/08/028/08/02

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