A 32-Gb/s C2C-DAC-Based PAM-4 Wireline Transmitter with Two-Tap Feed-Forward Equalization and Level-Mismatch Correction in 28-nm CMOS

Boyu Hu*, Yanghyo Kim, Rulin Huang, Yuan Du, Mau-Chung Chang

*Corresponding author for this work

Research output: Contribution to journalArticlepeer-review

3 Scopus citations

Abstract

This letter presents a C2C-DAC-based PAM-4 wireline transmitter that utilizes capacitor-weighting within a predriver stage for multitap multilevel signal summation in charge domain at the transmitter front end. Such a unique approach isolates the signal summing node from the output to alleviate bandwidth limitation and also inherently provides passive voltage-scaling and level-shifting at the predriver output without sacrificing its speed. A level-mismatch-correction scheme is adopted to effectively enhance PAM-4 signaling quality. Implemented in a 28-nm CMOS, the designed transmitter prototype achieves a peak data rate of 32 Gb/s and an energy efficiency of 2.1 mW/Gb/s.

Original languageEnglish
Article number8476164
Pages (from-to)1056-1058
Number of pages3
JournalIEEE Microwave and Wireless Components Letters
Volume28
Issue number11
DOIs
StatePublished - 1 Nov 2018

Keywords

  • C2C-DAC
  • feed-forward equalization
  • level-mismatch correction
  • PAM-4
  • transmitter

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