A 3.125 Gbps CMOS fully integrated optical receiver with adaptive analog equalizer

Wei-Zen Chen*, Shih Hao Huang, Guo Wei Wu, Chuan Chang Liu, Yang Tung Huang, Chin Fong Chiu, Wen Hsu Chang, Ying Zong Juang

*Corresponding author for this work

Research output: Chapter in Book/Report/Conference proceedingConference contribution

45 Scopus citations

Abstract

This paper presents the design of a 3.125 Gbps monolithic CMOS optical receiver, integrating a photo detector, a transimpedance amplifier, and a post limiting amplifier on a single chip. The optical receiver is capable of delivering 420 mVpp to 50 Ω output load after optical to electrical conversion. High speed operation is achieved by utilizing spatial modulated light (SML) detector and adaptive analog equalizer. Implemented in a 0.18 ?m CMOS technology, the total power dissipation is 175 mW. The chip size is 0.7 mm2.

Original languageEnglish
Title of host publication2007 IEEE Asian Solid-State Circuits Conference, A-SSCC
Pages396-399
Number of pages4
DOIs
StatePublished - 1 Dec 2007
Event2007 IEEE Asian Solid-State Circuits Conference, A-SSCC - Jeju, Korea, Republic of
Duration: 12 Nov 200714 Nov 2007

Publication series

Name2007 IEEE Asian Solid-State Circuits Conference, A-SSCC

Conference

Conference2007 IEEE Asian Solid-State Circuits Conference, A-SSCC
CountryKorea, Republic of
CityJeju
Period12/11/0714/11/07

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