A 300-mV 36-μW multiphase dual digital clock output generator with self-calibration

Ming Hung Chang*, Li Pu Chuang, I. Ming Chang, Wei Hwang

*Corresponding author for this work

Research output: Chapter in Book/Report/Conference proceedingConference contribution

1 Scopus citations

Abstract

A 300mV 20MHz-350MHz low variation all-digital multiphase dual clock output generator with rapid self-calibration has been designed with UMC 90nm CMOS technology model. The PVT immunity properties of several classic delay elements in low voltage era have been studied. A low voltage calibration unit is also proposed to reduce the maximum multiphase error no larger than 120ps when delay-locked loop is operating at 40MHz/300mV. A novel static current-mirrorbased phase blender is developed to provide wide range accurate twice multiphase information, and phase error is reduced by no more than 11.83%. The clock generator could provide more independent outputs by simply using additional edge combiner. The frequency and phase of output clock could be dynamically adjusted without relocking process. The total power dissipation of the all-digital multiphase dual digital clock output generator is 36μW at 40MHz/300mV.

Original languageEnglish
Title of host publication2008 IEEE International SOC Conference, SOCC
Pages97-100
Number of pages4
DOIs
StatePublished - 1 Dec 2008
Event2008 IEEE International SOC Conference, SOCC - Newport Beach, CA, United States
Duration: 17 Sep 200820 Sep 2008

Publication series

Name2008 IEEE International SOC Conference, SOCC

Conference

Conference2008 IEEE International SOC Conference, SOCC
CountryUnited States
CityNewport Beach, CA
Period17/09/0820/09/08

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    Chang, M. H., Chuang, L. P., Chang, I. M., & Hwang, W. (2008). A 300-mV 36-μW multiphase dual digital clock output generator with self-calibration. In 2008 IEEE International SOC Conference, SOCC (pp. 97-100). [4641487] (2008 IEEE International SOC Conference, SOCC). https://doi.org/10.1109/SOCC.2008.4641487