A 300-mm wafer-level three-dimensional integration scheme using tungsten through-silicon via and hybrid cu-adhesive bonding

F. Liu*, R. R. Yu, A. M. Young, J. P. Doyle, X. Wang, L. Shi, Kuan-Neng Chen, X. Li, D. A. Dipaola, D. Brown, C. T. Ryan, J. A. Hagan, K. H. Wong, M. Lu, X. Gu, N. R. Klymko, E. D. Perfecto, A. G. Merryman, K. A. Kelly, S. PurushothamanS. J. Koester, R. Wisnieff, W. Haensch

*Corresponding author for this work

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

74 Scopus citations

Abstract

A 300-mm wafer-level three-dimensional integration (3DI) process using tungsten (W) through-silicon vias (TSVs) and hybrid Cu/adhesive wafer bonding is demonstrated. The W TSVs have fine pitch (5 μm), small critical dimension (1.5 μm), and high aspect ratio (17:1). A hybrid Cu/adhesive bonding approach, also called transfer-join (TJ) method, is used to interconnect the TSVs to a Cu BEOL in a bottom wafer. The process also features thinning of the top wafer to 20 μm and a Cu backside BEOL on the thinned top wafer. The electrical and physical properties of the TSVs and bonded interconnect are presented and show RLC values that satisfy both the power delivery and high-speed signaling requirements for high-performance 3D systems.

Original languageEnglish
Title of host publication2008 IEEE International Electron Devices Meeting, IEDM 2008
DOIs
StatePublished - 1 Dec 2008
Event2008 IEEE International Electron Devices Meeting, IEDM 2008 - San Francisco, CA, United States
Duration: 15 Dec 200817 Dec 2008

Publication series

NameTechnical Digest - International Electron Devices Meeting, IEDM
ISSN (Print)0163-1918

Conference

Conference2008 IEEE International Electron Devices Meeting, IEDM 2008
CountryUnited States
CitySan Francisco, CA
Period15/12/0817/12/08

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