A 3-GHz, 22-ps/dec dynamic comparator using negative resistance combined with input pair

Bo Wei Chen*, Jen Peng Wang, Chia-Ming Tsai

*Corresponding author for this work

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

4 Scopus citations

Abstract

A high speed, low delay/log(ΔVin) dynamic comparator using negative resistance combined with input differential pair is proposed and designed in TSMC 90nm CMOS process technology. The delay/log(ΔVin) of the comparator is 22ps/dec and consumes 213μW at 3GHz clock rate and 1.2V supply. The standard deviation of the comparator input refer offset is 25mV.

Original languageEnglish
Title of host publicationProceedings of the 2010 Asia Pacific Conference on Circuit and System, APCCAS 2010
Pages648-651
Number of pages4
DOIs
StatePublished - 1 Dec 2010
Event2010 Asia Pacific Conference on Circuit and System, APCCAS 2010 - Kuala Lumpur, Malaysia
Duration: 6 Dec 20109 Dec 2010

Publication series

NameIEEE Asia-Pacific Conference on Circuits and Systems, Proceedings, APCCAS

Conference

Conference2010 Asia Pacific Conference on Circuit and System, APCCAS 2010
CountryMalaysia
CityKuala Lumpur
Period6/12/109/12/10

Keywords

  • Comparator
  • negative resistance
  • transconductance boosting

Fingerprint Dive into the research topics of 'A 3-GHz, 22-ps/dec dynamic comparator using negative resistance combined with input pair'. Together they form a unique fingerprint.

Cite this