A 3-10 GHz, 14 bands CMOS frequency synthesizer with spurs reduction for MB-OFDM UWB system

Tai You Lu*, Wei-Zen Chen

*Corresponding author for this work

Research output: Contribution to journalArticlepeer-review

12 Scopus citations

Abstract

This paper presents the design of a 14 bands CMOS frequency synthesizer with spurs reduction for MB-OFDM UWB system. Based on a single phase-locked loop and two-stage frequency mixing architecture, it alleviates harmonics mixing and frequency pulling to diminish spurs generation. Also, only divide-by-2 dividers are needed in the feedback path of the PLL. Thus more precise I/Q sub-harmonics can be derived for the SSB mixer in the 14 bands carrier generation. The image spurs are suppressed below -45 dBc and improved by more than 22 dB incorporating with I/Q calibration. Implemented in a 0.18-μm CMOS technology, this chip drains 65 mA from a single 1.8 V supply. The chip size is 2.5 by 2.2 mm 2 providing 14 bands I/Q phases.

Original languageEnglish
Article number5756216
Pages (from-to)948-958
Number of pages11
JournalIEEE Transactions on Very Large Scale Integration (VLSI) Systems
Volume20
Issue number5
DOIs
StatePublished - 1 May 2012

Keywords

  • Frequency synthesizer
  • I/Q calibration
  • multi-band orthogonal frequency division multiplexing (MB-OFDM) ultra-wide band (UWB)
  • phase-locked loop (PLL)
  • single-side band (SSB) mixer

Fingerprint Dive into the research topics of 'A 3-10 GHz, 14 bands CMOS frequency synthesizer with spurs reduction for MB-OFDM UWB system'. Together they form a unique fingerprint.

Cite this