A 2kb built-in row-controlled dynamic voltage scaling near-/sub-threshold FIFO memory for WBANs

Wei Hung Du*, Po-Tsang Huang, Ming Hung Chang, Wei Hwang

*Corresponding author for this work

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

1 Scopus citations

Abstract

Due to the limited energy source, ultra-low power designs are significant approaches in energy-constrained SoCs. In this paper, a 2kb built-in row-controlled dynamic voltage scaling (DVS) FIFO memory is proposed to adopt the operation voltage in the near-/sub-threshold regions for the WBAN (wireless body area network) system. The row-based DVS provides the fine-grained power switch control for each sub-block. Therefore, the switching energy can be reduced, and the switching setup time can be eliminated. Moreover, only one sub-block are operated in the typical mode, and other sub-blocks are operated in the low-power mode and cut-off mode for realizing the power saving. Based on TSMC 65nm technology, the proposed DVS FIFO can achieve 47.8% power saving.

Original languageEnglish
Title of host publication2012 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2012 - Proceedings of Technical Papers
DOIs
StatePublished - 25 Jul 2012
Event2012 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2012 - Hsinchu, Taiwan
Duration: 23 Apr 201225 Apr 2012

Publication series

Name2012 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2012 - Proceedings of Technical Papers

Conference

Conference2012 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2012
CountryTaiwan
CityHsinchu
Period23/04/1225/04/12

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