A 2GS/s 6b ADC in 0.18μm CMOS

Xicheng Jiang*, Zhengyu Wang, Mau-Chung Chang

*Corresponding author for this work

Research output: Contribution to journalConference article

61 Scopus citations

Abstract

A 2GS/s 6-bit ADC with time-interleaving is demonstrated in 0.18μm CMOS. Three cross-connected and pre-distorted reference voltages improve the averaging performance. Circuit techniques enabling an SNDR of 30dB at Nyquist input frequency and a FOM of 3.5pJ per conversion step are discussed, and experimental results validating the simulated performance metrics are presented.

Original languageEnglish
JournalDigest of Technical Papers - IEEE International Solid-State Circuits Conference
DOIs
StatePublished - 23 Jul 2003
Event2003 Digest of Technical Papers - , United States
Duration: 9 Feb 200313 Feb 2003

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