A 2.7Gb/s CDMA-interconnect transceiver chip set with multi-level signal data recovery for re-configurable VLSI systems

Zhiwei Xu*, Hyunchol Shin, Jongsun Kim, Mau-Chung Chang, Charles Chien

*Corresponding author for this work

Research output: Contribution to journalConference articlepeer-review

14 Scopus citations

Abstract

A 2.7Gb/s interconnect transceiver chip-set based on Code Division Multiple Access (CDMA) is described and implemented in 0.18μm CMOS technology to achieve real-time system re-configurability and multiple I/O communication. The transceiver chip-set, with an Alexander-type multi-level data recovery circuit, can reconfigure multiple I/O signal routes within a symbol period of 0.8ns. The chip-set dissipates 74mW and occupies 0.3mm 2 per I/O pair.

Original languageEnglish
JournalDigest of Technical Papers - IEEE International Solid-State Circuits Conference
DOIs
StatePublished - 23 Jul 2003
Event2003 Digest of Technical Papers - , United States
Duration: 9 Feb 200313 Feb 2003

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