A 2.7Gb/s interconnect transceiver chip-set based on Code Division Multiple Access (CDMA) is described and implemented in 0.18μm CMOS technology to achieve real-time system re-configurability and multiple I/O communication. The transceiver chip-set, with an Alexander-type multi-level data recovery circuit, can reconfigure multiple I/O signal routes within a symbol period of 0.8ns. The chip-set dissipates 74mW and occupies 0.3mm 2 per I/O pair.
|Journal||Digest of Technical Papers - IEEE International Solid-State Circuits Conference|
|State||Published - 23 Jul 2003|
|Event||2003 Digest of Technical Papers - , United States|
Duration: 9 Feb 2003 → 13 Feb 2003