A 2.5Gbps serial-link data transceiver in a 0.35 μm digital CMOS technology

Wei-Zen Chen*, Meng Chih Weng

*Corresponding author for this work

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

Abstract

This paper presents the design of a single chip serial link data transceiver. Incorporating with 8 to 1 multiplexer and 1 to 8 demultiplexer, the transceiving data rate ranges from 640 Mbps to 2.56 Gbps. In the transmitter side, a novel precharged type multiplexer is proposed to minimize deterministic jitter. In the receiver side, an over-sampling data recovery loop utilizing mixed-signal phase picking scheme is adopted for data resynchronization and demultiplexing. A novel phase interpolator with resistive averaging technique is proposed to generate uniformly distributed sampling phases over wide frequency range, so as to improve bit error rate performance. For data packet size less than 1000 bytes, the tolerated frequency offset between transmitter and receiver is about 1.3 % by a built in elastic buffer. The measured data jitter at the transmitter side after multiplexing is 5.8 ps (rms), and is 43.3 ps (rms) at the receiver side after demultiplexing. The measured bit error rate for 2.5 Gbps data receiving is about 10-10. Fabricated in a 035μm digital CMOS process, this chip occupies 2.9 mm × 2.4 mm. The total power consumption is 280 mW under 2V supply.

Original languageEnglish
Title of host publicationProceedings of 2004 IEEE Asia-Pacific Conference on Advanced System Integrated Circuits
Pages232-235
Number of pages4
DOIs
StatePublished - 1 Dec 2004
EventProceedings of 2004 IEEE Asia-Pacific Conference on Advanced System Integrated Circuits - Fukuoka, Japan
Duration: 4 Aug 20045 Aug 2004

Publication series

NameProceedings of 2004 IEEE Asia-Pacific Conference on Advanced System Integrated Circuits

Conference

ConferenceProceedings of 2004 IEEE Asia-Pacific Conference on Advanced System Integrated Circuits
CountryJapan
CityFukuoka
Period4/08/045/08/04

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