A 2.5Gbps CMOS data serializer

Meng Tzer Wong, Wei-Zen Chen

Research output: Chapter in Book/Report/Conference proceedingConference contribution

5 Scopus citations

Abstract

This paper describes the design of a 2.5 Gbps CMOS data serializer, including a low jitter multiphase phase-locked loop, a multiplexer, and an output buffer. High speed parallel to serial data conversion is toggled by the multiphase PLL. This serializer achieves a conversion rate of up to 312.5 Mbyte/s and a transmission speed of 2.5 Gbps. The measured RMS jitter is less than 6 ps from a 2.5 Gbps data output. The measured eye diagram meets OC-48 transition mask. Die size is 1062 μmx1020 μm.

Original languageEnglish
Title of host publication2002 IEEE Asia-Pacific Conference on ASIC, AP-ASIC 2002 - Proceedings
PublisherInstitute of Electrical and Electronics Engineers Inc.
Pages73-76
Number of pages4
ISBN (Electronic)0780373634, 9780780373631
DOIs
StatePublished - 1 Jan 2002
Event3rd IEEE Asia-Pacific Conference on ASIC, AP-ASIC 2002 - Taipei, Taiwan
Duration: 6 Aug 20028 Aug 2002

Publication series

Name2002 IEEE Asia-Pacific Conference on ASIC, AP-ASIC 2002 - Proceedings

Conference

Conference3rd IEEE Asia-Pacific Conference on ASIC, AP-ASIC 2002
CountryTaiwan
CityTaipei
Period6/08/028/08/02

Keywords

  • Data serializer
  • parallel-in-serial-out (PISO)
  • phase-locked loop (PLL)

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