@inproceedings{f94af07e220d41f2a584e2d976108b1d,
title = "A 2.5Gbps CMOS data serializer",
abstract = "This paper describes the design of a 2.5 Gbps CMOS data serializer, including a low jitter multiphase phase-locked loop, a multiplexer, and an output buffer. High speed parallel to serial data conversion is toggled by the multiphase PLL. This serializer achieves a conversion rate of up to 312.5 Mbyte/s and a transmission speed of 2.5 Gbps. The measured RMS jitter is less than 6 ps from a 2.5 Gbps data output. The measured eye diagram meets OC-48 transition mask. Die size is 1062 μmx1020 μm.",
keywords = "Data serializer, parallel-in-serial-out (PISO), phase-locked loop (PLL)",
author = "Wong, {Meng Tzer} and Wei-Zen Chen",
year = "2002",
month = jan,
day = "1",
doi = "10.1109/APASIC.2002.1031535",
language = "English",
series = "2002 IEEE Asia-Pacific Conference on ASIC, AP-ASIC 2002 - Proceedings",
publisher = "Institute of Electrical and Electronics Engineers Inc.",
pages = "73--76",
booktitle = "2002 IEEE Asia-Pacific Conference on ASIC, AP-ASIC 2002 - Proceedings",
address = "United States",
note = "null ; Conference date: 06-08-2002 Through 08-08-2002",
}