A 2.5Gbps CMOS data serializer

Meng Tzer Wong; Wei-Zen Chen

doi:10.1109/APASIC.2002.1031535

A 2.5Gbps CMOS data serializer

Meng Tzer Wong, Wei-Zen Chen

Institute of Electronics

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

5 Scopus citations

Abstract

This paper describes the design of a 2.5 Gbps CMOS data serializer, including a low jitter multiphase phase-locked loop, a multiplexer, and an output buffer. High speed parallel to serial data conversion is toggled by the multiphase PLL. This serializer achieves a conversion rate of up to 312.5 Mbyte/s and a transmission speed of 2.5 Gbps. The measured RMS jitter is less than 6 ps from a 2.5 Gbps data output. The measured eye diagram meets OC-48 transition mask. Die size is 1062 μmx1020 μm.

Original language	English
Title of host publication	2002 IEEE Asia-Pacific Conference on ASIC, AP-ASIC 2002 - Proceedings
Publisher	Institute of Electrical and Electronics Engineers Inc.
Pages	73-76
Number of pages	4
ISBN (Electronic)	0780373634, 9780780373631
DOIs	https://doi.org/10.1109/APASIC.2002.1031535
State	Published - 1 Jan 2002
Event	3rd IEEE Asia-Pacific Conference on ASIC, AP-ASIC 2002 - Taipei, Taiwan Duration: 6 Aug 2002 → 8 Aug 2002

Publication series

Name	2002 IEEE Asia-Pacific Conference on ASIC, AP-ASIC 2002 - Proceedings

Conference

Conference	3rd IEEE Asia-Pacific Conference on ASIC, AP-ASIC 2002
Country	Taiwan
City	Taipei
Period	6/08/02 → 8/08/02

Keywords

Data serializer
parallel-in-serial-out (PISO)
phase-locked loop (PLL)

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10.1109/APASIC.2002.1031535

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title = "A 2.5Gbps CMOS data serializer",

abstract = "This paper describes the design of a 2.5 Gbps CMOS data serializer, including a low jitter multiphase phase-locked loop, a multiplexer, and an output buffer. High speed parallel to serial data conversion is toggled by the multiphase PLL. This serializer achieves a conversion rate of up to 312.5 Mbyte/s and a transmission speed of 2.5 Gbps. The measured RMS jitter is less than 6 ps from a 2.5 Gbps data output. The measured eye diagram meets OC-48 transition mask. Die size is 1062 μmx1020 μm.",

keywords = "Data serializer, parallel-in-serial-out (PISO), phase-locked loop (PLL)",

author = "Wong, {Meng Tzer} and Wei-Zen Chen",

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doi = "10.1109/APASIC.2002.1031535",

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series = "2002 IEEE Asia-Pacific Conference on ASIC, AP-ASIC 2002 - Proceedings",

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note = "null ; Conference date: 06-08-2002 Through 08-08-2002",

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Wong, MT & Chen, W-Z 2002, A 2.5Gbps CMOS data serializer. in 2002 IEEE Asia-Pacific Conference on ASIC, AP-ASIC 2002 - Proceedings., 1031535, 2002 IEEE Asia-Pacific Conference on ASIC, AP-ASIC 2002 - Proceedings, Institute of Electrical and Electronics Engineers Inc., pp. 73-76, 3rd IEEE Asia-Pacific Conference on ASIC, AP-ASIC 2002, Taipei, Taiwan, 6/08/02. https://doi.org/10.1109/APASIC.2002.1031535

A 2.5Gbps CMOS data serializer. / Wong, Meng Tzer; Chen, Wei-Zen.

2002 IEEE Asia-Pacific Conference on ASIC, AP-ASIC 2002 - Proceedings. Institute of Electrical and Electronics Engineers Inc., 2002. p. 73-76 1031535 (2002 IEEE Asia-Pacific Conference on ASIC, AP-ASIC 2002 - Proceedings).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

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AB - This paper describes the design of a 2.5 Gbps CMOS data serializer, including a low jitter multiphase phase-locked loop, a multiplexer, and an output buffer. High speed parallel to serial data conversion is toggled by the multiphase PLL. This serializer achieves a conversion rate of up to 312.5 Mbyte/s and a transmission speed of 2.5 Gbps. The measured RMS jitter is less than 6 ps from a 2.5 Gbps data output. The measured eye diagram meets OC-48 transition mask. Die size is 1062 μmx1020 μm.

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KW - phase-locked loop (PLL)

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Y2 - 6 August 2002 through 8 August 2002

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A 2.5Gbps CMOS data serializer

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