A 2.56 Gb/s Soft RS (255, 239) decoder chip for optical communication systems

Yi Min Lin, Chih Hsiang Hsu, Hsie-Chia Chang, Chen-Yi Lee

Research output: Contribution to journalArticle

10 Scopus citations

Abstract

Due to high transmission rate requirement for optical communication systems, the growing uncertainty of received signals results in the limited transmission distance. In this paper, a decision-confined soft RS decoder chip is proposed to enhance the error correcting performance with area-efficient architectures. Instead of generating numerous possible candidate codewords and determining the most likely one as output codeword, our approach produces only one codeword by confining the degree of error location polynomial. Therefore, hardware complexity is significantly reduced by eliminating decision making unit. Moreover, an iteration-reduced RiBM algorithm is provided to enlarge the coding gain by using more least reliable positions (LRPs) in the limited operation latency. According to simulation results, our proposed soft RS (255, 239; 8) decoder with 5 LRPs outperforms 0.4 dB at 10-4 codeword error rate (CER) as compared to hard RS decoders. Implemented in standard CMOS 90 nm technology, the soft decoder chip can achieve 2.56 Gb/s throughput with similar complexity as a hard decoder. It can fit well for 10-40 Gb/s with 16 RS decoders in optical fiber systems and 2.5 Gb/s GPON applications.

Original languageEnglish
Article number6731597
Pages (from-to)2110-2118
Number of pages9
JournalIEEE Transactions on Circuits and Systems I: Regular Papers
Volume61
Issue number7
DOIs
StatePublished - 1 Jan 2014

Keywords

  • Error correction code
  • Reed-Solomon (RS) code
  • optical communication

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