A 252kgate/71mW multi-standard multi-channel video decoder for high definition video applications

Chih Da Chien*, Chien Chang Lin, Yi Hung Shih, He Chun Chen, Chia Jui Huang, Cheng Yen Yu, Chin Liang Chen, Ching Hwa Cheng, Jiun-In  Guo

*Corresponding author for this work

Research output: Chapter in Book/Report/Conference proceedingConference contribution

52 Scopus citations

Abstract

A multi-standard (JPEG/MPEG-1/2/4/H.264) video decoder includes 252kgates and 4.9kB internal memory in a core size of 4.2×1.2mm2 using 0.13μm 1P8M CMOS. The power consumption at 1.2V supply is 71mW at 120MHz for real-time HD1080 and 7.9mW at 20MHz for real-time H.264 decoding of D1 video.

Original languageEnglish
Title of host publication2007 IEEE International Solid-State Circuits Conference, ISSCC - Digest of Technical Papers
DOIs
StatePublished - 27 Sep 2007
Event54th IEEE International Solid-State Circuits Conference, ISSCC 2007 - San Francisco, CA, United States
Duration: 11 Feb 200715 Feb 2007

Publication series

NameDigest of Technical Papers - IEEE International Solid-State Circuits Conference
ISSN (Print)0193-6530

Conference

Conference54th IEEE International Solid-State Circuits Conference, ISSCC 2007
CountryUnited States
CitySan Francisco, CA
Period11/02/0715/02/07

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    Chien, C. D., Lin, C. C., Shih, Y. H., Chen, H. C., Huang, C. J., Yu, C. Y., Chen, C. L., Cheng, C. H., & Guo, J-I. (2007). A 252kgate/71mW multi-standard multi-channel video decoder for high definition video applications. In 2007 IEEE International Solid-State Circuits Conference, ISSCC - Digest of Technical Papers [4242375] (Digest of Technical Papers - IEEE International Solid-State Circuits Conference). https://doi.org/10.1109/ISSCC.2007.373404