A 2.5-V 14-bit 180-mW cascaded Σ△ ADC for ADSL2+ applications

Teng Hung Chang*, Lan-Rong Dung, Jwin Yen Guo, Kai Jiun Yang

*Corresponding author for this work

Research output: Contribution to conferencePaperpeer-review

Abstract

This paper presents a sigma-delta (Σ △) analog-todigital converter (ADC) for the extended bandwidth asymmetric digital subscriber line application (ADSL2+). The core of the ADC is a cascaded 2-1-1 Σ△ modulator that employs a resonator-based topology in the first stage, three tri-level quantizers, and two different pairs of reference voltages. As shown in the experimental result, for a 2.2 MHz signal bandwidth, the ADC achieves a dynamic range of 86 dB and a peak signal-to-noise and distortion ratio (SNDR) of 78 dB with an oversampling ratio of 16. It is implemented in a 0.25-μm CMOS technology, in a 2.4mm 2 active area including decimation filter and reference voltage buffers, and dissipates 180 mW from a 2.5-V power supply.

Original languageEnglish
Pages59-62
Number of pages4
DOIs
StatePublished - 1 Dec 2006
Event2006 IEEE Asian Solid-State Circuits Conference, ASSCC 2006 - Hangzhou, China
Duration: 13 Nov 200615 Nov 2006

Conference

Conference2006 IEEE Asian Solid-State Circuits Conference, ASSCC 2006
CountryChina
CityHangzhou
Period13/11/0615/11/06

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