A 2.5-V 14-bit, 180-mW cascaded ΣΔ ADC for ADSL2+ application

Teng Hung Chang*, Lan-Rong Dung, Jwin Yen Guo, Kai Jiun Yang

*Corresponding author for this work

Research output: Contribution to journalArticlepeer-review

13 Scopus citations

Abstract

This paper presents a sigma-delta ΣΔ analog-to-digital converter (ADC) for the extended bandwidth asymmetric digital subscriber line application. The core of the ADC is a cascaded 2-1-1 ΣΔ modulator that employs a resonator-based topology in the first stage, three tri-level quantizers, and two different pairs of reference voltages. As shown in the experimental result, for a 2.2-MHz signal bandwidth, the ADC achieves a dynamic range of 86 dB and a peak signal-to-noise and distortion ratio of 78 dB with an oversampling ratio of 16. It is implemented in a 0.25-μm CMOS technology, in a 2.8 mm 2 active area including decimation filter and reference voltage buffers, and dissipates 180 mW from a 2.5-V power supply.

Original languageEnglish
Article number4362085
Pages (from-to)2357-2368
Number of pages12
JournalIEEE Journal of Solid-State Circuits
Volume42
Issue number11
DOIs
StatePublished - 1 Nov 2007

Keywords

  • Analog-to-digital conversion
  • Asymmetric digital subscriber line (ADSL)
  • Multistage
  • Resonator-based topology
  • sigma-delta ΣΔ modulation

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