A 25-ns 1-Mbit CMOS SRAM with Loading-Free Bit Lines

Masataka Matsui, Takayuki Ohtani, Jun Ichi Tsujimoto, Hiroshi Iwai, Azuma Suzuki, Katsuhiko Sato, Mitsuo Isobe, Kazuhiko Hashimoto, Mitsuchika Saitoh, Hideki Shibata, Hisayo Sasaki, Tadashi Matsuno, Jun Ichi Matsunaga, Tetsuya Iizuka

Research output: Contribution to journalArticle

13 Scopus citations

Abstract

A 128K× 8-bit CMOS SRAM is described which achieves a 25-ns access time, less than 40-mA active current at 10 MHz, and 2-µA standby current. The novel bit-line circuitry (loading-free bit line), using two kinds of NMOSFET's with different threshold voltages, improves bit-line signal speed and integrity. The two-stage local amplification technique minimizes the data-line delay. The dynamic double-word-line scheme (DDWL) allows the cell array to be divided into 32 sections along the word-line direction without a huge increase in chip area. This allows the DDWL scheme to reduce the core-area delay time and operating power to about half that of other conventional structures. A double-metal 0.8-µm twin-tub CMOS technology has been developed to realize the 5.6 × 9.5-µm2 cell size and the 6.86 × 15.37-mm2 chip size.

Original languageEnglish
Pages (from-to)733-740
Number of pages8
JournalIEEE Journal of Solid-State Circuits
Volume22
Issue number5
DOIs
StatePublished - Oct 1987

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    Matsui, M., Ohtani, T., Tsujimoto, J. I., Iwai, H., Suzuki, A., Sato, K., Isobe, M., Hashimoto, K., Saitoh, M., Shibata, H., Sasaki, H., Matsuno, T., Matsunaga, J. I., & Iizuka, T. (1987). A 25-ns 1-Mbit CMOS SRAM with Loading-Free Bit Lines. IEEE Journal of Solid-State Circuits, 22(5), 733-740. https://doi.org/10.1109/JSSC.1987.1052807