A 25-Gb/s, -10.8-dBm input sensitivity, PD-bandwidth tolerant CMOS optical receiver

Shih Hao Huang, Wei-Zen Chen

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

4 Scopus citations

Abstract

This paper describes a 25-Gb/s energy-efficient CMOS optical receiver with high input sensitivity. By incorporating a current boosting preamplifier with time-interleaved integrating-type optical receiver, it also circumvents CID issue with high PD bandwidth tolerance. Experimental results show that the receiver can achieve 25-Gb/s operation by integrating with a 9-GHz or 17-GHz GaAs PD. Input sensitivities in the two cases are -7.2 dBm (w/i 9-GHz PD) and -10.8 dBm (w/i 17-GHz PD) respectively for BER of less than 10-12. The energy efficiency is 1.13 pJ/bit. Fabricated in TSMC 40-nm CMOS technology, the core circuit occupies a chip area of 0.007 mm2 only.

Original languageEnglish
Title of host publication2015 Symposium on VLSI Circuits, VLSI Circuits 2015
PublisherInstitute of Electrical and Electronics Engineers Inc.
PagesC120-C121
ISBN (Electronic)9784863485020
DOIs
StatePublished - 31 Aug 2015
Event29th Annual Symposium on VLSI Circuits, VLSI Circuits 2015 - Kyoto, Japan
Duration: 17 Jun 201519 Jun 2015

Publication series

NameIEEE Symposium on VLSI Circuits, Digest of Technical Papers
Volume2015-August

Conference

Conference29th Annual Symposium on VLSI Circuits, VLSI Circuits 2015
CountryJapan
CityKyoto
Period17/06/1519/06/15

Keywords

  • comparator
  • current amplifier
  • decision feedback equalizer
  • optical receiver

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