A 3 V, single chip optical receiver analog front-end capable of operating at 2.5 Gbit/sec is fabricated in a 0.35 μ m CMOS technology. The IC contains a TIA with 54.5 dBΩ conversion gain, f -3dB of 2.5 GHz, and a limiting amplifier with a conversion gain of 42 dB, f -3db of 2.3 GHz. The TIA is DC coupled to the limiting amplifier. The measured eye diagram meet OC-48 transition mask. Input referred noise current is about 800 nA.
|Number of pages||4|
|Journal||Proceedings of the Custom Integrated Circuits Conference|
|State||Published - 1 Jan 2002|