A 2.4-Gsample/s DVFS FFT processor for MIMO OFDM communication systems

Yuan Chen*, Yu Wei Lin, Yu Chi Tsao, Chen-Yi Lee

*Corresponding author for this work

Research output: Contribution to journalArticlepeer-review

68 Scopus citations

Abstract

This paper presents a new dynamic voltage and frequency scaling (DVFS) FFT processor for MIMO OFDM applications. By the proposed multimode multipath-delay-feedback (MMDF) architecture, our FFT processor can process 1-8-stream 256-point FFTs or a high-speed 256-point FFT in two processing domains at minimum clock frequency for DVFS operations. A parallelized radix-24 FFT algorithm is also employed to save the power consumption and hardware cost of complex multipliers. Furthermore, a novel open-loop voltage detection and scaling (OLVDS) mechanism is proposed for fast and robust voltage management. With these schemes, the proposed FFT processor can operate at adequate voltage/frequency under different configurations to support the power-aware feature. A test chip of the proposed FFT processor has been fabricated using UMC 90 nm single-poly nine-metal CMOS process with a core area of 1.88 × 1.88 mm2. The SQNR performance of this FFT chip is over 35.8 dB for QPSK/16-QAM modulation. Power dissipation of 2.4 Gsample/s 256-point FFT computations is about 119.7 mW at 0.85 V. Depending on the operation mode, power can be saved by 18%-43% with voltage scaling in TT corner.

Original languageEnglish
Article number4494644
Pages (from-to)1260-1273
Number of pages14
JournalIEEE Journal of Solid-State Circuits
Volume43
Issue number5
DOIs
StatePublished - 1 May 2008

Keywords

  • Dynamic voltage and frequency scaling (DVFS)
  • Fast Fourier transform (FFT)
  • Multiple-input multiple-output (MIMO)
  • Orthogonal frequency division multiplexing (OFDM)

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