A 24 GHz Low-power and High-gain Low-noise Amplifier Using 0.18 mu m CMOS Technology for FMCW Radar Applications

Chun Yi Lin, Ming Wei Lin, Ching Piao Liang, Shyh-Jong Chung

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

In this paper, a low power and high gain low-noise amplifier (LNA) is presented for 24 GHz FMCW radar applications fabricated in a 0.18 mu m RF CMOS process. The proposed LNA is with the characteristics of the source inductive degeneration type, the current reuse technique, and the invariance of current density in CMOS process. The proposed LNA with a compact size has a gain of 18.95 dB and a noise figure of 5.8 dB, while consuming 11.3 mW. The measured input 1-dB compression point (IP1 dB) and an input third-order intercept point (IIP3) are -26 dBm and -16.5 dBm, respectively.
Original languageEnglish
Title of host publicationProgress in Electromagnetics Research Symposium
PublisherElectromagnetics Academy
Pages892-896
Number of pages5
StatePublished - 2012

Keywords

  • DESIGN

Fingerprint Dive into the research topics of 'A 24 GHz Low-power and High-gain Low-noise Amplifier Using 0.18 mu m CMOS Technology for FMCW Radar Applications'. Together they form a unique fingerprint.

  • Cite this

    Lin, C. Y., Lin, M. W., Liang, C. P., & Chung, S-J. (2012). A 24 GHz Low-power and High-gain Low-noise Amplifier Using 0.18 mu m CMOS Technology for FMCW Radar Applications. In Progress in Electromagnetics Research Symposium (pp. 892-896). Electromagnetics Academy.