A 2.4-GHz low-flicker-noise CMOS sub-harmonic receiver

Jin Siang Syu*, Chin-Chun Meng, Chia Ling Wang

*Corresponding author for this work

Research output: Contribution to journalArticlepeer-review

14 Scopus citations

Abstract

A 2.4-GHz low-noise sub-harmonic direct-conversion receiver (SH-DCR) is demonstrated using standard 0.18-μ m CMOS technology. Deep-n-well vertical-NPN (V-NPN) bipolar junction transistors (BJTs) are employed to solve the flicker noise problem in CMOS process. Design optimization of a power-constrained noise-impedance-matched low-noise amplifier (LNA) with the effect of lossy on-chip inductors is fully discussed in this paper. A multi-stage octet-phase polyphase filter is analyzed in detail and implemented to generate well balanced octet-phase LO signals. As a result, the demonstrated receiver achieves 51-dB voltage gain and 3-dB noise figure with flicker noise corner less than 30 kHz when RF = 2.4 GHz. The I/Q amplitude/phase mismatch is below ±0.2 dB±1° , respectively, covering from 2.35 to 2.6 GHz. The dc current consumption is 5 mA at a 1.8-V supply.

Original languageEnglish
Article number6419865
Pages (from-to)437-447
Number of pages11
JournalIEEE Transactions on Circuits and Systems I: Regular Papers
Volume60
Issue number2
DOIs
StatePublished - 11 Feb 2013

Keywords

  • Direct-conversion receiver (DCR)
  • low-noise amplifier (LNA)
  • octet-phase
  • sub-harmonic mixer (SHM)
  • vertical-NPN (V-NPN)

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