A 24-GHz High Linearity Down-conversion Mixer in 90-nm CMOS

Feifei Chen, Yunshan Wang, Jung Lin Lin, Zuo-Min Tsai , Huei Wang

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

A 24-GHz high linearity down-conversion mixer in 90-nm CMOS is presented in this paper. The mixer utilizes folded architecture, LC tank, distributed derivative superposition (DS) linearization technique to achieve high linearity with relatively low power. The mixer achieves 0 dBm IP_1\mathbfdB. The mixer provides-3 dB conversion gain and the IIP 3 is 21 dBm with only 10-mW dc consumption.

Original languageEnglish
Title of host publication2018 IEEE International Symposium on Radio-Frequency Integration Technology, RFIT 2018
PublisherInstitute of Electrical and Electronics Engineers Inc.
ISBN (Electronic)9781538659717
DOIs
StatePublished - 5 Nov 2018
Event2018 IEEE International Symposium on Radio-Frequency Integration Technology, RFIT 2018 - Melbourne, Australia
Duration: 15 Aug 201817 Aug 2018

Publication series

Name2018 IEEE International Symposium on Radio-Frequency Integration Technology, RFIT 2018

Conference

Conference2018 IEEE International Symposium on Radio-Frequency Integration Technology, RFIT 2018
CountryAustralia
CityMelbourne
Period15/08/1817/08/18

Keywords

  • CMOS
  • folded architecture
  • mixer

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  • Cite this

    Chen, F., Wang, Y., Lin, J. L., Tsai , Z-M., & Wang, H. (2018). A 24-GHz High Linearity Down-conversion Mixer in 90-nm CMOS. In 2018 IEEE International Symposium on Radio-Frequency Integration Technology, RFIT 2018 [8524128] (2018 IEEE International Symposium on Radio-Frequency Integration Technology, RFIT 2018). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/RFIT.2018.8524128