A 2.37Gb/s 284.8mW rate-compatible (491,3,6) LDPC-CC decoder

Chih Lung Chen*, Yu Hsiang Lin, Hsie-Chia Chang, Chen-Yi Lee

*Corresponding author for this work

Research output: Chapter in Book/Report/Conference proceedingConference contribution

4 Scopus citations

Abstract

In this paper, a (491, 3, 6) time-varying LDPC-CC decoder chip supporting five code-rates is implemented in 90nm CMOS technology. The decoder containing 5 processors occupies 2.24mm2 and provides twice faster decoding convergence speed. Maximum throughput 2.37Gb/s is measured under 1.2V supply with a 0.024nJ/bit/proc energy efficiency.

Original languageEnglish
Title of host publication2011 Symposium on VLSI Circuits, VLSIC 2011 - Digest of Technical Papers
Pages134-135
Number of pages2
StatePublished - 16 Sep 2011
Event2011 Symposium on VLSI Circuits, VLSIC 2011 - Kyoto, Japan
Duration: 15 Jun 201117 Jun 2011

Publication series

NameIEEE Symposium on VLSI Circuits, Digest of Technical Papers

Conference

Conference2011 Symposium on VLSI Circuits, VLSIC 2011
CountryJapan
CityKyoto
Period15/06/1117/06/11

Keywords

  • high throughput
  • LDPC-CC

Fingerprint Dive into the research topics of 'A 2.37Gb/s 284.8mW rate-compatible (491,3,6) LDPC-CC decoder'. Together they form a unique fingerprint.

  • Cite this

    Chen, C. L., Lin, Y. H., Chang, H-C., & Lee, C-Y. (2011). A 2.37Gb/s 284.8mW rate-compatible (491,3,6) LDPC-CC decoder. In 2011 Symposium on VLSI Circuits, VLSIC 2011 - Digest of Technical Papers (pp. 134-135). [5986073] (IEEE Symposium on VLSI Circuits, Digest of Technical Papers).