A 23.6-38.3GHz Low-Noise PLL with Digital Ring Oscillator and Multi-Ratio Injection-Locked Dividers for Millimeter-Wave Sensing

Yan Zhang, Yan Zhao, Rulin Huang, Chia Jen Liang, Ching Wen Chiang, Yen Cheng Kuan, Mau Chung Frank Chang

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

Abstract

This paper presents a 23.6-38.3GHz cascaded PLL with quadrature phases designed and prototyped in 28nm CMOS. Unlike conventional approaches, no on-chip inductor is used for millimeter-wave frequency generation. Instead, a simple inverter-based ring oscillator, with scaled copies of itself and explicit mixers, forms a unique VCO-and-multi-ratio-injection-locked-frequency-divider subsystem suitable for ultra-wide frequency synthesis. The prototype achieves comparable noise performance to its LC-VCO-based counterparts for similar applications. The phase noise is better than-96dBc/Hz at 1MHz offset across the entire range with power consumption less than 35mW. This PLL is intended for integrated wide-band sensing applications at Ka-and W-bands (with an additional frequency tripler).

Original languageEnglish
Title of host publicationRFIC 2020 - 2020 IEEE Radio Frequency Integrated Circuits Symposium
PublisherInstitute of Electrical and Electronics Engineers Inc.
Pages3-6
Number of pages4
ISBN (Electronic)9781728168098
DOIs
StatePublished - Aug 2020
Event2020 IEEE Radio Frequency Integrated Circuits Symposium, RFIC 2020 - Virtual, Los Angeles, United States
Duration: 4 Aug 20206 Aug 2020

Publication series

NameDigest of Papers - IEEE Radio Frequency Integrated Circuits Symposium
Volume2020-August
ISSN (Print)1529-2517

Conference

Conference2020 IEEE Radio Frequency Integrated Circuits Symposium, RFIC 2020
CountryUnited States
CityVirtual, Los Angeles
Period4/08/206/08/20

Keywords

  • injection-locked oscillators
  • phase locked loops
  • ring oscillators
  • spectroscopy

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