A 22-ns 1-Mbit CMOS High-Speed DRAM with Address Multiplexing

Nicky C.C. Lu, Gary B. Bronner, Walter H. Henkels, Sang H. Dhong, Robert L. Franch, Wei Hwang, Frank L. Pesavento, T. V. Rajeevakumar, Koji Kitamura, Yasunori Iguchi, Eiji Yano, Roy E. Scheuerlein, Yasunao Katayama, Toshiaki Kirihata, Hideto Niijima, Motoo Nishiwaki, Yoshinori Sakaue, Yasusuke Suzuki

Research output: Contribution to journalArticlepeer-review

12 Scopus citations


This paper describes a I-Mbit high-speed DRAM (HSDRAM), which has a nominal random access time of less than 27 ns and a column access time of 12 ns with address multiplexing. A doublepolysilicon double-metal CMOS technology having PMOS arrays inside n-wells was developed with an average 1.3-μm feature size. The chip has also been fabricated in a 0.9 X shrunken version with an area of 67 mm2, showing a 22-ns access time. The chip power consumption is lower than 500 mW at 60-ns cycle time. This HSDRAM, which provides SRAM-like speed while retaining DRAM-like density, allows DRAM’s to be used in a broad new range of applications.

Original languageEnglish
Pages (from-to)1198-1205
Number of pages8
JournalIEEE Journal of Solid-State Circuits
Issue number5
StatePublished - 1 Jan 1989

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