A 22-ns 1-Mbit CMOS High-Speed DRAM with Address Multiplexing

Nicky C.C. Lu; Gary B. Bronner; Walter H. Henkels; Sang H. Dhong; Robert L. Franch; Wei Hwang; Frank L. Pesavento; T. V. Rajeevakumar; Koji Kitamura; Yasunori Iguchi; Eiji Yano; Roy E. Scheuerlein; Yasunao Katayama; Toshiaki Kirihata; Hideto Niijima; Motoo Nishiwaki; Yoshinori Sakaue; Yasusuke Suzuki

doi:10.1109/JSSC.1989.572579

A 22-ns 1-Mbit CMOS High-Speed DRAM with Address Multiplexing

Nicky C.C. Lu, Gary B. Bronner, Walter H. Henkels, Sang H. Dhong, Robert L. Franch, Wei Hwang, Frank L. Pesavento, T. V. Rajeevakumar, Koji Kitamura, Yasunori Iguchi, Eiji Yano, Roy E. Scheuerlein, Yasunao Katayama, Toshiaki Kirihata, Hideto Niijima, Motoo Nishiwaki, Yoshinori Sakaue, Yasusuke Suzuki

International College of Semiconductor Technology

Research output: Contribution to journal › Article › peer-review

12 Scopus citations

Abstract

This paper describes a I-Mbit high-speed DRAM (HSDRAM), which has a nominal random access time of less than 27 ns and a column access time of 12 ns with address multiplexing. A doublepolysilicon double-metal CMOS technology having PMOS arrays inside n-wells was developed with an average 1.3-μm feature size. The chip has also been fabricated in a 0.9 X shrunken version with an area of 67 mm², showing a 22-ns access time. The chip power consumption is lower than 500 mW at 60-ns cycle time. This HSDRAM, which provides SRAM-like speed while retaining DRAM-like density, allows DRAM’s to be used in a broad new range of applications.

Original language	English
Pages (from-to)	1198-1205
Number of pages	8
Journal	IEEE Journal of Solid-State Circuits
Volume	24
Issue number	5
DOIs	https://doi.org/10.1109/JSSC.1989.572579
State	Published - 1 Jan 1989

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Lu, N. C. C., Bronner, G. B., Henkels, W. H., Dhong, S. H., Franch, R. L., Hwang, W., Pesavento, F. L., Rajeevakumar, T. V., Kitamura, K., Iguchi, Y., Yano, E., Scheuerlein, R. E., Katayama, Y., Kirihata, T., Niijima, H., Nishiwaki, M., Sakaue, Y., & Suzuki, Y. (1989). A 22-ns 1-Mbit CMOS High-Speed DRAM with Address Multiplexing. IEEE Journal of Solid-State Circuits, 24(5), 1198-1205. https://doi.org/10.1109/JSSC.1989.572579

Lu, Nicky C.C. ; Bronner, Gary B. ; Henkels, Walter H. ; Dhong, Sang H. ; Franch, Robert L. ; Hwang, Wei ; Pesavento, Frank L. ; Rajeevakumar, T. V. ; Kitamura, Koji ; Iguchi, Yasunori ; Yano, Eiji ; Scheuerlein, Roy E. ; Katayama, Yasunao ; Kirihata, Toshiaki ; Niijima, Hideto ; Nishiwaki, Motoo ; Sakaue, Yoshinori ; Suzuki, Yasusuke. / A 22-ns 1-Mbit CMOS High-Speed DRAM with Address Multiplexing. In: IEEE Journal of Solid-State Circuits. 1989 ; Vol. 24, No. 5. pp. 1198-1205.

@article{5f8a79f49245458f8bd2c98df8ed1195,

title = "A 22-ns 1-Mbit CMOS High-Speed DRAM with Address Multiplexing",

abstract = "This paper describes a I-Mbit high-speed DRAM (HSDRAM), which has a nominal random access time of less than 27 ns and a column access time of 12 ns with address multiplexing. A doublepolysilicon double-metal CMOS technology having PMOS arrays inside n-wells was developed with an average 1.3-μm feature size. The chip has also been fabricated in a 0.9 X shrunken version with an area of 67 mm2, showing a 22-ns access time. The chip power consumption is lower than 500 mW at 60-ns cycle time. This HSDRAM, which provides SRAM-like speed while retaining DRAM-like density, allows DRAM{\textquoteright}s to be used in a broad new range of applications.",

author = "Lu, {Nicky C.C.} and Bronner, {Gary B.} and Henkels, {Walter H.} and Dhong, {Sang H.} and Franch, {Robert L.} and Wei Hwang and Pesavento, {Frank L.} and Rajeevakumar, {T. V.} and Koji Kitamura and Yasunori Iguchi and Eiji Yano and Scheuerlein, {Roy E.} and Yasunao Katayama and Toshiaki Kirihata and Hideto Niijima and Motoo Nishiwaki and Yoshinori Sakaue and Yasusuke Suzuki",

year = "1989",

month = jan,

day = "1",

doi = "10.1109/JSSC.1989.572579",

language = "English",

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Lu, NCC, Bronner, GB, Henkels, WH, Dhong, SH, Franch, RL, Hwang, W, Pesavento, FL, Rajeevakumar, TV, Kitamura, K, Iguchi, Y, Yano, E, Scheuerlein, RE, Katayama, Y, Kirihata, T, Niijima, H, Nishiwaki, M, Sakaue, Y & Suzuki, Y 1989, 'A 22-ns 1-Mbit CMOS High-Speed DRAM with Address Multiplexing', IEEE Journal of Solid-State Circuits, vol. 24, no. 5, pp. 1198-1205. https://doi.org/10.1109/JSSC.1989.572579

A 22-ns 1-Mbit CMOS High-Speed DRAM with Address Multiplexing. / Lu, Nicky C.C.; Bronner, Gary B.; Henkels, Walter H.; Dhong, Sang H.; Franch, Robert L.; Hwang, Wei; Pesavento, Frank L.; Rajeevakumar, T. V.; Kitamura, Koji; Iguchi, Yasunori; Yano, Eiji; Scheuerlein, Roy E.; Katayama, Yasunao; Kirihata, Toshiaki; Niijima, Hideto; Nishiwaki, Motoo; Sakaue, Yoshinori; Suzuki, Yasusuke.

In: IEEE Journal of Solid-State Circuits, Vol. 24, No. 5, 01.01.1989, p. 1198-1205.

Research output: Contribution to journal › Article › peer-review

TY - JOUR

T1 - A 22-ns 1-Mbit CMOS High-Speed DRAM with Address Multiplexing

AU - Lu, Nicky C.C.

AU - Bronner, Gary B.

AU - Henkels, Walter H.

AU - Dhong, Sang H.

AU - Franch, Robert L.

AU - Hwang, Wei

AU - Pesavento, Frank L.

AU - Rajeevakumar, T. V.

AU - Kitamura, Koji

AU - Iguchi, Yasunori

AU - Yano, Eiji

AU - Scheuerlein, Roy E.

AU - Katayama, Yasunao

AU - Kirihata, Toshiaki

AU - Niijima, Hideto

AU - Nishiwaki, Motoo

AU - Sakaue, Yoshinori

AU - Suzuki, Yasusuke

PY - 1989/1/1

Y1 - 1989/1/1

N2 - This paper describes a I-Mbit high-speed DRAM (HSDRAM), which has a nominal random access time of less than 27 ns and a column access time of 12 ns with address multiplexing. A doublepolysilicon double-metal CMOS technology having PMOS arrays inside n-wells was developed with an average 1.3-μm feature size. The chip has also been fabricated in a 0.9 X shrunken version with an area of 67 mm2, showing a 22-ns access time. The chip power consumption is lower than 500 mW at 60-ns cycle time. This HSDRAM, which provides SRAM-like speed while retaining DRAM-like density, allows DRAM’s to be used in a broad new range of applications.

AB - This paper describes a I-Mbit high-speed DRAM (HSDRAM), which has a nominal random access time of less than 27 ns and a column access time of 12 ns with address multiplexing. A doublepolysilicon double-metal CMOS technology having PMOS arrays inside n-wells was developed with an average 1.3-μm feature size. The chip has also been fabricated in a 0.9 X shrunken version with an area of 67 mm2, showing a 22-ns access time. The chip power consumption is lower than 500 mW at 60-ns cycle time. This HSDRAM, which provides SRAM-like speed while retaining DRAM-like density, allows DRAM’s to be used in a broad new range of applications.

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M3 - Article

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JO - IEEE Journal of Solid-State Circuits

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