A 2.2 Gb/s DQPSK basehand receiver in 90-nm CMOS for 60 GHz wireless links

Minghui Chen*, Mau-Chung Chang

*Corresponding author for this work

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

3 Scopus citations

Abstract

This paper presents a CMOS DQPSK direct-conversion baseband receiver that can deliver 2.2 Gb/s data rate to support 1920×1080 interlaced HDTV wireless transmission in the unlicensed 60 GHz band. The receiver system architecture and major circuit blocks are described. Implemented in the 90nm CMOS process, the receiver achieves a maximum data rate of 2.4 Gb/s with measured BER of 10-9. It is operated under 1V DC supply voltage with 85 m W of total power consumption.

Original languageEnglish
Title of host publication2007 Symposium on VLSI Circuits, VLSIC - Digest of Technical Papers
Pages56-57
Number of pages2
DOIs
StatePublished - 1 Dec 2007
Event2007 Symposium on VLSI Circuits, VLSIC - Kyoto, Japan
Duration: 14 Jun 200716 Jun 2007

Publication series

NameIEEE Symposium on VLSI Circuits, Digest of Technical Papers

Conference

Conference2007 Symposium on VLSI Circuits, VLSIC
CountryJapan
CityKyoto
Period14/06/0716/06/07

Keywords

  • Bang-bang PLL
  • Baseband
  • Differential QPSK
  • Direct-conversion receiver
  • Multi-level clock recovery

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