A 22-dBm 24-GHz power amplifier using 0.18-μm CMOS technology

Pin Cheng Huang*, Jing Lin Kuo, Zuo-Min Tsai , Kun You Lin, Huei Wang

*Corresponding author for this work

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

34 Scopus citations

Abstract

A fully integrated 24-GHz 22-dBm power amplifier was designed and fabricated in 0.18-Jlm CMOS technology. Optimized device size selection and resonance matching techniques are adopted in this single stage power amplifier design. High pass matching circuit is used to reduce output losses and maintain gain flatness. T he measurement results shows a 22 dBm of saturation power and 20 dBm of output power at 1 dB compression point with peak PAE of 20% under 3.6 V bias supply. To the best of author's knowledge, this PA demonstrates the highest output power and highest PAE at 1 dB compression among the reported CMOS PAs in this frequency range.

Original languageEnglish
Title of host publication2010 IEEE MTT-S International Microwave Symposium, MTT 2010
Pages248-251
Number of pages4
DOIs
StatePublished - 15 Oct 2010
Event2010 IEEE MTT-S International Microwave Symposium, MTT 2010 - Anaheim, CA, United States
Duration: 23 May 201028 May 2010

Publication series

NameIEEE MTT-S International Microwave Symposium Digest
ISSN (Print)0149-645X

Conference

Conference2010 IEEE MTT-S International Microwave Symposium, MTT 2010
CountryUnited States
CityAnaheim, CA
Period23/05/1028/05/10

Keywords

  • Cascode
  • CMOS
  • Power amplifiers

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