A (21150, 19050) GC-LDPC Decoder for NAND flash applications

Yen Chin Liao*, Chien Lin, Hsie-Chia Chang, Shu Lin

*Corresponding author for this work

Research output: Contribution to journalArticle

4 Scopus citations

Abstract

In this paper, a (21150, 19050) globally-coupled low-density parity check (GC-LDPC) code designed for NAND flash memories is presented. The proposed LDPC code comprises three disjoint subcodes which can be decoded independently. This highly structural parity check matrix contributes to efficient decoder implementation and flexible decoding flow control. Moreover, a two-phase local/global decoding procedure optimized for the proposed GC-LDPC code is introduced. Scenarios of collaborative decoding that leverages the special code structures are discussed. In the proposed decoder architecture, the pipelined processing elements with scheduling are employed to reduce the critical path and decoding latency as well. Implemented in UMC 65 nm process, the post-layout simulation shows a maximum decoding throughput of 4.32 Gb/s with the chip area 3.376 mm 2 .

Original languageEnglish
Article number8528505
Pages (from-to)1219-1230
Number of pages12
JournalIEEE Transactions on Circuits and Systems I: Regular Papers
Volume66
Issue number3
DOIs
StatePublished - 1 Mar 2019

Keywords

  • Globally-coupled LDPC codes
  • emerging memory ECC
  • two-phase local/global iterative decoding

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