A 210-GHz amplifier in 40-nm digital CMOS technology

Chun Lin Ko, Chun Hsing Li, Chien-Nan Kuo, Ming Ching Kuo, Da Chiang Chang

Research output: Contribution to journalArticlepeer-review

25 Scopus citations


This paper presents a 210-GHz amplifier design in 40-nm digital bulk CMOS technology. The theoretical maximum voltage gain that an amplifier can achieve and the loss of a matching network are derived for the optimization of a few hundred gigahertz amplifiers. Accordingly, the bias and size of transistors, circuit topology, and inter-stage coupling method can be determined methodically to maximize the amplifier gain. The measured results show that the amplifier exhibits a peak power gain of 10.5 dB at 213.5 GHz and an estimated 3-dB bandwidth of 13 GHz. The power consumption is only 42.3 mW under a 0.8-V supply. To the best of the authors' knowledge, this work demonstrates the CMOS amplifier with highest operation frequency reported thus far.

Original languageEnglish
Article number6516105
Pages (from-to)2438-2446
Number of pages9
JournalIEEE Transactions on Microwave Theory and Techniques
Issue number6
StatePublished - 20 May 2013


  • Amplifier
  • maximum gain
  • shunt stub matching
  • transmission line

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